llvm-svn: 160110

llvm-svn: 159959

subtarget CPU descriptions and support new features of
MachineScheduler.

MachineModel has three categories of data:
1) Basic properties for coarse grained instruction cost model.
2) Scheduler Read/Write resources for simple per-opcode and operand cost model (TBD).
3) Instruction itineraties for detailed per-cycle reservation tables.

These will all live side-by-side. Any subtarget can use any
combination of them. Instruction itineraries will not change in the
near term. In the long run, I expect them to only be relevant for
in-order VLIW machines that have complex contraints and require a
precise scheduling/bundling model. Once itineraries are only actively
used by VLIW-ish targets, they could be replaced by something more
appropriate for those targets.

This tablegen backend rewrite sets things up for introducing
MachineModel type #2: per opcode/operand cost model.

llvm-svn: 159891

llvm-svn: 159890

llvm-svn: 159889

'|&' bash syntax. We have lots of users with a bash on their system
which doesn't support this syntax, and as bash is still significantly
faster, we should support them.

The test suite has already been updated to cope with this.

llvm-svn: 159580

llvm-svn: 159543

Reapplies r159406 with minor cleanup. The regressions appear to have been spurious.

llvm-svn: 159541

This is directly cloned from the logic in the TCL test bits of lit.
Hopefully will fix most of the windows build bot fallout.

llvm-svn: 159528

This reverts commit r159406. I noticed a performance regression so I'll back out for now.

llvm-svn: 159411

The TargetInstrInfo::getNumMicroOps API does not change, but soon it
will be used by MachineScheduler. Now each subtarget can specify the
number of micro-ops per itinerary class. For ARM, this is currently
always dynamic (-1), because it is used for load/store multiple which
depends on the number of register operands.

Zero is now a valid number of micro-ops. This can be used for
nop pseudo-instructions or instructions that the hardware can squash
during dispatch.

llvm-svn: 159406

llvm-svn: 159334

llvm-svn: 159316

Patch by Ivan Llopard!

llvm-svn: 159281

Don't override a custom diagnostic w/ a generic InvalidOperand, all else
being equal.

llvm-svn: 159238

Support the following intrinsics:
llvm.x86.avx2.gather.d.pd, llvm.x86.avx2.gather.q.pd
llvm.x86.avx2.gather.d.pd.256, llvm.x86.avx2.gather.q.pd.256
llvm.x86.avx2.gather.d.ps, llvm.x86.avx2.gather.q.ps
llvm.x86.avx2.gather.d.ps.256, llvm.x86.avx2.gather.q.ps.256

Modified Disassembler to handle VSIB addressing mode.

llvm-svn: 159221

When generating selection tables for Pat instances, TableGen relied on
an output Instruction's Pattern field being set to infer whether a
chain should be added.

This patch adds additional logic to check various flag fields so that
correct code can be generated even if Pattern is unset.

llvm-svn: 159217

llvm-svn: 159178

"Invalid operand" may be a completely correct diagnostic, but it's often
insufficiently specific to really help identify and fix the problem in
assembly source. Allow a target to specify a more-specific diagnostic kind
for each AsmOperandClass derived definition and use that to provide
more detailed diagnostics when an operant of that class resulted in a
match failure.

rdar://8987109

llvm-svn: 159050

Original commit message:
    Allow up to 64 functional units per processor itinerary.

    This patch changes the type used to hold the FU bitset from unsigned to uint64_t.
    This will be needed for some upcoming PowerPC itineraries.

llvm-svn: 159027

llvm-svn: 159017

llvm-svn: 159014

This makes it explicit when ScoreboardHazardRecognizer will be used.
"GenericItineraries" would only make sense if it contained real
itinerary values and still required ScoreboardHazardRecognizer.

llvm-svn: 158963

llvm-svn: 158730

This patch changes the type used to hold the FU bitset from unsigned to uint64_t.
This will be needed for some upcoming PowerPC itineraries.

llvm-svn: 158679

When returning a 'cannot match due to missing CPU features' error code,
if there are multiple potential matches with different feature sets,
return the smallest set of missing features from the alternatives as
that's most likely to be the one that's desired.

llvm-svn: 158673

There is otherwise not a newline between the CPU name and the start of the next
pass's output which makes both difficult to read.

llvm-svn: 158350

The TableGenBackend base class doesn't do much, and will be removed
completely soon.

Patch by Sean Silva!

llvm-svn: 158311

This fixes an accidental dependence on static initialization order that I introduced yesterday.

Thank you Lang!!!

llvm-svn: 158215

Teach the AsmMatcherEmitter to allow InstAlias' where the suboperands of a complex operand are called out explicitly in the asm string.

llvm-svn: 158183

llvm-svn: 158101

LLVM is now -Wunused-private-field clean except for
- lib/MC/MCDisassembler/Disassembler.h. Not sure why it keeps all those unaccessible fields.
- gtest.

llvm-svn: 158096

There are some that I didn't remove this round because they looked like
obvious stubs. There are dead variables in gtest too, they should be
fixed upstream.

llvm-svn: 158090

llvm-svn: 158046

This allows a subtarget to explicitly specify the issue width and
other properties without providing pipeline stage details for every
instruction.

llvm-svn: 157979

llvm-svn: 157885

llvm-svn: 157756

Each register unit has one or two root registers. The full set of
registers containing a given register unit can be computed as the union
of the root registers and their super-registers.

Provide an MCRegUnitRootIterator class to enumerate the roots.

llvm-svn: 157753

It seems I broke C++11.

llvm-svn: 157711

llvm-svn: 157684