LiveIntervals::findLiveInMBBs has to do a full binary search for each segment.

llvm-svn: 129292

llvm-svn: 129287

Both coalescing and register allocation already check aliases for interference,
so these extra segments are only slowing us down.

This speeds up both linear scan and the greedy register allocator.

llvm-svn: 129283

This particularly helps with the initial transfer of fixed intervals.

llvm-svn: 129277

llvm-svn: 129276

In particular, don't repeatedly recompute the PIC base live range after rematerialization.

llvm-svn: 129275

llvm-svn: 129271

Switch lowering probably shouldn't be using FP for this.  This resolves PR9581.

llvm-svn: 129199

It is common for large live ranges to have few basic blocks with register uses
and many live-through blocks without any uses. This approach grows the Hopfield
network incrementally around the use blocks, completely avoiding checking
interference for some through blocks.

llvm-svn: 129188

This doesn't require seeking in the live interval union, so it is very cheap.

llvm-svn: 129187

with undef arguments.

llvm-svn: 129185

Simplify array bound checks and clarify comments.  One element array can have same non-zero number as lower bound as well as upper bound.

llvm-svn: 129170

If lower bound is more then upper bound then consider it is an unbounded array.
An array is unbounded if non-zero lower bound is same as upper bound.
If lower bound and upper bound are zero than array has one element.

llvm-svn: 129156

Change -arm-trap-func= into a non-arm specific option. Now Intrinsic::trap is lowered into a call to the specified trap function at sdisel time.

llvm-svn: 129152

of { i32, void ()* }. Teach the verifier to verify that, deleting copies of
checks strewn about.

llvm-svn: 129128

induction variable. The preRA scheduler is unaware of induction vars,
so we look for potential "virtual register cycles" instead.

Fixes <rdar://problem/8946719> Bad scheduling prevents coalescing

llvm-svn: 129100

PHI values may be deleted, causing the flags to be wrong. This fixes PR9616.

llvm-svn: 129092

llvm-svn: 129081

llvm-svn: 129080

llvm-svn: 129079

llvm-svn: 129044

llvm-svn: 129030

Without any positive bias, there is nothing for the spill placer to to. It will
spill everywhere.

llvm-svn: 129029

If there are no positive nodes, the algorithm can be aborted early.

llvm-svn: 129021

This will allow us to abort the algorithm early if it is determined to be futile.

llvm-svn: 129020

llvm-svn: 128986

About 90% of the relevant blocks are live-through without uses, and the only
information required about them is their number. This saves memory and enables
later optimizations that need to look at only the use-blocks.

llvm-svn: 128985

llvm-svn: 128963

llvm-svn: 128962

Treat the landing pad as a normal successor when that happens.

llvm-svn: 128961

llvm-svn: 128947

llvm-svn: 128935

llvm-svn: 128929

of a basic block.

llvm-svn: 128925

When dead code elimination removes all but one use, try to fold the single def into the remaining use.

Rematerialization can leave single-use loads behind that we might as well fold whenever possible.

llvm-svn: 128918

llvm-svn: 128914

There can be multiple defs for a single virtual register when they are defining
sub-registers.

The missing <dead> flag was stopping the inline spiller from eliminating dead
code after rematerialization.

llvm-svn: 128888

llvm-svn: 128887

This allows us to always keep the smaller slot for an instruction which is what
we want when a register has early clobber defines.

Drop the UsingInstrs set and the UsingBlocks map. They are no longer needed.

llvm-svn: 128886

llvm-svn: 128875