Commits · 19ac75364fc9fb49158dd17cd56ae55b4b6fa726 · Roger Ferrer / llvm-epi · GitLab

Jul 15, 2022
- [PGO] Improve hash-mismatch warning message · 19ac7536
  Rong Xu authored Jul 15, 2022
  19ac7536
- [LSR] Allow already invariant operand for ICmpZero matching [try 2] · 6ab686eb
  Philip Reames authored Jul 15, 2022
  6ab686eb
- [Reassociate] Enable FP reassociation via 'reassoc' and 'nsz' · c6507930
  Warren Ristow authored Jul 15, 2022
  c6507930
- [AMDGPU] Add remarks to output some resource usage · 67357739
  Vang Thao authored Mar 11, 2022
  67357739
- Revert "[LSR] Allow already invariant operand for ICmpZero matching" · 6fe766be
  Philip Reames authored Jul 15, 2022
  6fe766be
- [LV] Use umax(VF * UF, MinProfTC) for scalable vectors. · aa00fb02
  Florian Hahn authored Jul 15, 2022
  aa00fb02
- [LSR] Allow already invariant operand for ICmpZero matching · 9153515a
  Philip Reames authored Jul 15, 2022
  9153515a
- Re-apply 5acd4716 , Add a shared-memory based orc::MemoryMapper, with fixes. · 32d8d23c
  Anubhab Ghosh authored Jul 15, 2022
  32d8d23c
- [NFC][SCEV] Rename variable to correspond its current meaning · 883e83d5
  Max Kazantsev authored Jul 15, 2022
  
  883e83d5
- [SCEV] List all binops in getOperandsToCreate() · 2659e1bf
  Nikita Popov authored Jul 15, 2022
  2659e1bf
- [DAG] Move "xor (X logical_shift ShiftC), XorC --> (not X) logical_shift... · 3c8bf296
  Simon Pilgrim authored Jul 15, 2022
  3c8bf296
- [stackmaps] Legalise patchpoint arguments. · 2e62a26f
  Edd Barrett authored Jul 15, 2022
  2e62a26f
- [AMDGPU][MC][NFC] Remove unnecessary code · 185c36de
  Dmitry Preobrazhensky authored Jul 15, 2022
  185c36de
- [AMDGPU][MC][GFX11] Correct disassembly of *_e64_dpp opcodes which support op_sel · 2a6532d5
  Dmitry Preobrazhensky authored Jul 15, 2022
  2a6532d5
- [InstCombine] Ensure constant folding in binop of select fold · 8a519b3c
  Nikita Popov authored Jul 15, 2022
  8a519b3c
- [LV][NFC] Fix the condition for printing debug messages · bd404fbc
  Mel Chen authored Jul 15, 2022
  bd404fbc
- Modernize Optional::{getValueOr,hasValue} · 3c849d0a
  Fangrui Song authored Jul 15, 2022
  
  3c849d0a
- [IR] Don't use blockaddresses as callbr arguments · 2a721374
  Nikita Popov authored Jul 07, 2022
  2a721374
- [LSR] Create SCEVExpander earlier, use member isSafeToExpand() (NFC) · f75ccadc
  Nikita Popov authored Jul 14, 2022
  f75ccadc
- [llvm] A macro of if should be wrapped in do ... while (false) · 9510d597
  owenca authored Jul 15, 2022
  
  9510d597
- [RISCV] Add cost model for vector.reverse mask operation · dca821d8
  Lian Wang authored Jun 29, 2022
  dca821d8
- [Orc] Honor hasJIT in JITTargetMachineBuilder::createTargetMachine · 8922adf6
  Rainer Orth authored Jul 15, 2022
  8922adf6
- [Sparc] Don't claim JIT support on SPARC for now · 09c1ee10
  Rainer Orth authored Jul 15, 2022
  09c1ee10
- [X86] Use generic tuning for "x86-64" if "tune-cpu" is not specified · 190518da
  Phoebe Wang authored Jul 15, 2022
  190518da
- [RISCV] Refine the heuristics for our custom (mul (and X, C2), C1) isel. · 79016f6e
  Craig Topper authored Jul 14, 2022
  79016f6e
- [RISCV] Fix mistake in RISCVTTIImpl::getIntImmCostInst. · bc0d6565
  Craig Topper authored Jul 14, 2022
  bc0d6565
- [AMDGPU] Update the mechanism used to check for cycles and add eges in power-sched mutation · 8a12f20e
  jeff authored Jul 13, 2022
  
  8a12f20e
- [llvm-dwp] Add SHF_COMPRESSED support and remove .zdebug support · 141c9d77
  Fangrui Song authored Jul 14, 2022
  141c9d77
- [SelectionDAG][RISCV][AMDGPU][ARM] Improve SimplifyDemandedBits for SHL with variable shift amount. · dcfc1fd2
  Craig Topper authored Jul 14, 2022
  dcfc1fd2
- [RISCV] Make TuneSiFive7 depend on TuneNoDefaultUnroll instead of listing it for every SiFive7 CPU · 9913ea49
  Craig Topper authored Jul 14, 2022
  
  9913ea49
- Remove zlibgnu support in llvm-mc · d63ec445
  David Blaikie authored Jul 14, 2022
  d63ec445
Jul 14, 2022
- [AMDGPU] Lowering VGPR to SGPR copies to v_readfirstlane_b32 if profitable. · 2e29b013
  Alexander Timofeev authored Jun 21, 2022
  2e29b013
- [clang][CodeGen] add fn_ret_thunk_extern to synthetic fns · 140bfdca
  Nick Desaulniers authored Jul 14, 2022
  140bfdca
- [GlobalISel] Change widenScalar of G_FCONSTANT to mutate into G_CONSTANT. · d4f84df0
  Amara Emerson authored Jul 14, 2022
  d4f84df0
- [RISCV] Add a RISCV specific CodeGenPrepare pass. · 1a8468ba
  Craig Topper authored Jul 14, 2022
  1a8468ba
- [MachineCombiner] Don't compute the latency of transient instructions · 2f11b3a6
  Guozhi Wei authored Jul 14, 2022
  2f11b3a6
- [SimplifyIndVar] Use enum class for ExtendKind. NFC · 0e718443
  Craig Topper authored Jul 14, 2022
  0e718443
- [SCEV] Avoid creating unnecessary SCEVs for SelectInsts. · e7ec1746
  Florian Hahn authored Jul 14, 2022
  e7ec1746
- [RISCV] Disable subregister liveness by default · d1a5669f
  Fraser Cormack authored Jul 13, 2022
  d1a5669f
- [SCEVExpander] Allow udiv with isKnownNonZero(RHS) + add vscale case · 3bc09c7d
  Philip Reames authored Jul 14, 2022
  3bc09c7d