llvm-svn: 231412

NFC.

llvm-svn: 231411

The test case fails on AArch64.

llvm-svn: 231410

It's not that easy. If we're only checking -fsanitize=shift-base we
still need to verify that exponent has sane value, otherwise
UBSan-inserted checks for base will contain undefined behavior
themselves.

llvm-svn: 231409

This patch reduces code size for all AVX targets and increases speed for some chips.

SSE 4.1 introduced the useless (see code comments) 2-register form of BLENDV and
only in the packed float/double flavors.

AVX subsequently made the instruction useful by adding a 4-register operand form.

So we just need to paper over the lack of scalar forms of this instruction, complicate
the code to choose float or double forms, and use blendv on scalars since all FP is in
xmm registers anyway.

This gives us an approximately 50% speed up for a blendv microbenchmark sequence
on SandyBridge and Haswell:
blendv : 29.73 cycles/iter
logic : 43.15 cycles/iter

No new test cases with this patch because:

1. fast-isel-select-sse.ll tests the positive side for regular X86 lowering and fast-isel
2. sse-minmax.ll and fp-select-cmp-and.ll confirm that we're not firing for scalar selects without AVX
3. fp-select-cmp-and.ll and logical-load-fold.ll confirm that we're not firing for scalar selects with constants.

http://llvm.org/bugs/show_bug.cgi?id=22483

Differential Revision: http://reviews.llvm.org/D8063

llvm-svn: 231408

Trying to get the build green so we can notice new failures easier.

Differential Revision: http://reviews.llvm.org/D8039

llvm-svn: 231407

NFC intended.

llvm-svn: 231406

llvm-svn: 231405

llvm-svn: 231404

llvm-svn: 231403

caller of the function.

llvm-svn: 231402

The copies already diverged, don't let them become any worse. Reduce
redundancy in code with a little macro metaprogramming.

llvm-svn: 231401

Fixes PR22761, rdar://20024866.
Differential Revision: http://reviews.llvm.org/D8042

llvm-svn: 231400

These are focused around the actual relocation rewriting itself, not the rest of the infrastructure.

llvm-svn: 231399

I missed an occurrence of the old symbol in my previous patch.

llvm-svn: 231398

This is what all the targets check for and is consistent with the
initialized value of MissingFeatures, which is sometimes assinged
to ErrorInfo.

llvm-svn: 231397

This commit enables forming vector extloads for ARM.
It only does so for legal types, and when we can't fold the extension
in a wide/long form of the user instruction.

Enabling it for larger types isn't as good an idea on ARM as it is on
X86, because: 
- we pretend that extloads are legal, but end up generating vld+vmov
- we have instructions like vld {dN, dM}, which can't be generated
  when we "manually expand" extloads to vld+vmov.

For legal types, the combine doesn't fire that often: in the
integration tests only in a big endian testcase, where it removes a
pointless AND.

Related to rdar://19723053
Differential Revision: http://reviews.llvm.org/D7423

llvm-svn: 231396

We maintain a map from symbols to archive files for the archive file
pre-loading. That map is created at the beginning of the resolve()
and is never updated. However, the input file list may be updated by
File::beforeLink(). This is a patch to update the map after beforeLink.

llvm-svn: 231395

Summary:
LLDB driver was simply tacking quotes around the strings in lldb commands, hoping that will work.
This changes it to properly escape quotes and backslashes.

Reviewers: clayborg

Subscribers: lldb-commits

Differential Revision: http://reviews.llvm.org/D8083

llvm-svn: 231394

Changes call to PrintStackTrace(FILE*) to call
PrintStackTrace(raw_ostream&)

llvm-svn: 231393

This will be followed by a change on the clang side to update
the only user of this function with the new version.

Differential Revision: http://reviews.llvm.org/D8074
Reviewed By: Reid Kleckner

llvm-svn: 231392

llvm-svn: 231391

This removes yet another custom label to mark the start of a function.

llvm-svn: 231390

We know that the absolute symbol will be less than 2GB and thus will
always fit.

llvm-svn: 231389

llvm-svn: 231388

The first element of STACKFRAME64 is a struct and Clang wants us to put
braces around it's initialization. Instead, drop the zero. The result
should be the same.

llvm-svn: 231387

Turns out it's pretty straightforward and simplifies the implementation.

Reviewers: andrew.w.kaylor

Differential Revision: http://reviews.llvm.org/D8051

llvm-svn: 231386

Revert r231276 (including r231277): Add a lock() function in PassRegistry to speed up multi-thread synchronization.

llvm-svn: 231385

llvm-svn: 231384

llvm-svn: 231383

llvm::sys::PrintBacktrace(FILE*) is supposed to print a backtrace
of the current thread given the current PC.  This function was
unimplemented on Windows, and instead the only time we could
print a backtrace was as the result of an exception through
LLVMUnhandledExceptionFilter.

This patch implements backtracing of self by using
RtlCaptureContext to get a CONTEXT for the current thread, and
moving the printing and StackWalk64 code to a common method that
printing own stack trace and printing stack trace of an exception
can use.

Differential Revision: http://reviews.llvm.org/D8068
Reviewed by: Reid Kleckner

llvm-svn: 231382

llvm-svn: 231381

Currently shuffles may only be combined if they are of the same type, despite the fact that bitcasts are often introduced in between shuffle nodes (e.g. x86 shuffle type widening).

This patch allows a single input shuffle to peek through bitcasts and if the input is another shuffle will merge them, shuffling using the smallest sized type, and re-applying the bitcasts at the inputs and output instead.

Dropped old ShuffleToZext test - this patch removes the use of the zext and vector-zext.ll covers these anyhow.

Differential Revision: http://reviews.llvm.org/D7939

llvm-svn: 231380

llvm-svn: 231379

While reviewing the changes to Clang to add builtin support for the vsld, vsrd, and vsrad instructions, it was pointed out that the builtins are generating the LLVM opcodes (shl, lshr, and ashr) not calls to the intrinsics. This patch changes the implementation of the vsld, vsrd, and vsrad instructions from from intrinsics to VXForm_1 instructions and makes them legal with P8 Altivec. It also removes the definition of the int_ppc_altivec_vsld, int_ppc_altivec_vsrd, and int_ppc_altivec_vsrad intrinsics.

llvm-svn: 231378

Rework reverse_iterator::operator[] so as not to use the base iterators operator [], which can cause constness problems. Fixes PR17883

llvm-svn: 231375

llvm-svn: 231374

We need to reinterpret float/double types as uint/ulong in order to
perform the bitwise operations.

This has been tested with piglit, OpenCV, and the ocl conformance tests.

v2:
  - Use vector operations rather than splitting vectors into scalar
    components.

Reviewed-by: Aaron Watry <awatry@gmail.com>
llvm-svn: 231373

Added lowering for ISD::CONCAT_VECTORS and ISD::INSERT_SUBVECTOR for i1 vectors,
it is needed to pass all masked_memop.ll tests for SKX.

llvm-svn: 231371

llvm-svn: 231370