Commits · 5c7ec998a916baf8b35d571d0cc11753d464792d · Roger Ferrer / llvm-epi · GitLab

May 11, 2022
- [test, riscv] Add test illustrating missing handling for fallthrough blocks in 541c9ba8 · ca81c0f8
  Philip Reames authored May 11, 2022
  
  ca81c0f8
- [RISCV] Add caching to the gather/scatter to strided load/store conversion. · f499ec6b
  Craig Topper authored May 11, 2022
  f499ec6b
- [riscv] Canonicalize vsetvli (vsetvli avl, vtype1) vtype2 transitionsas reviewed · 72925d98
  Philip Reames authored May 11, 2022
  72925d98
- [riscv] Add tests for vsetvli reuse across iterations of a loop · 98736234
  Philip Reames authored May 11, 2022
  98736234
- [riscv] Prefer to use previous VL for scalar move instructionsK · cc0283a6
  Philip Reames authored May 11, 2022
  cc0283a6
- [RISCV] Make PseudoReadVL have the vtypes of the corresponding VLEFF/VLSEGFF. · 4537aae0
  Yeting Kuo authored May 08, 2022
  4537aae0
- [RISCV] Add rvv codegen support for vp.fpext. · 2509dcd5
  Jianjian GUAN authored Apr 18, 2022
  2509dcd5
May 10, 2022
- Revert "[RISCV][SelectionDAG] Support VECREDUCE_ADD mask operation" · f14a1f26
  Lian Wang authored May 10, 2022
  f14a1f26
- [RISCV][SelectionDAG] Support VECREDUCE_ADD mask operation · 17a8a1bb
  Lian Wang authored May 09, 2022
  17a8a1bb
- [RISCV] Add more tests for vector reduce mask operations · 3b3ff240
  Lian Wang authored May 10, 2022
  3b3ff240
May 09, 2022
- [riscv] Add a few more vsetvli insertion tests · 11728db9
  Philip Reames authored May 09, 2022
  11728db9
- [riscv] Fix state tracking bug on vsetvli (phi of vsetvli) peephole · 7ed16e7c
  Philip Reames authored May 09, 2022
  7ed16e7c
May 06, 2022
- [RISCV] Add an extra vsetvli insertion test · 588155aa
  Fraser Cormack authored May 06, 2022
  588155aa
- [RISCV][SelectionDAG] Support VP_REDUCE_ADD mask operation. · fb0d636f
  Lian Wang authored May 05, 2022
  fb0d636f
May 05, 2022
- [riscv] Use X0 for destination of VSETVLI instruction if result unused · 042a7a5f
  Philip Reames authored May 05, 2022
  042a7a5f
- [RISCV] Use movImm went multiplying by simm12 in getVLENFactoredAmount. · 60cb4896
  Craig Topper authored May 04, 2022
  60cb4896
May 04, 2022
- [RISCV] Add a special case to treat riscv-v-vector-bits-min=-1 as meaning use Zvl*b value. · 411bb42e
  Craig Topper authored May 04, 2022
  411bb42e
- [RISCV] Add a test showing incorrect VSETVLI insertion · 78c1dcbf
  Fraser Cormack authored Apr 20, 2022
  78c1dcbf
- [RISCV] Update isLegalAddressingMode for RVV. · 1d6430b9
  Craig Topper authored May 03, 2022
  1d6430b9
- [RISCV] Make use of SHXADD instructions in RVV spill/reload code. · 9cce9a12
  Craig Topper authored May 03, 2022
  9cce9a12
- [riscv] Add vsetvli tests involving moves to/from scalar regs · dbe716e8
  Philip Reames authored May 03, 2022
  
  dbe716e8
- [riscv] Add a couple more vsetvli tests · dbbbc9e2
  Philip Reames authored May 03, 2022
  
  dbbbc9e2
May 03, 2022
- [RISCV] Fix incorrect codegen for masked vmsge{u}.vx with mask agnostic. · 5807e59a
  Zakk Chen authored May 02, 2022
  5807e59a
Apr 30, 2022
- [RISCV] Add DAGCombine to fold base operation and reduction. · c069e370
  Yeting Kuo authored Mar 27, 2022
  c069e370
Apr 28, 2022
- [RISCV] Fix alias printing for vmnot.m · 8631a5e7
  Craig Topper authored Apr 28, 2022
  8631a5e7
- [RISCV] Support VP_SETCC mask operations · dc0ae8ce
  Lian Wang authored Apr 26, 2022
  dc0ae8ce
Apr 27, 2022
- [RISCV][RVV] Select unmasked TU RVV pseudos in a DAG post-process · 6b55f133
  ShihPo Hung authored Mar 21, 2022
  6b55f133
- [RISCV] Precommit test for D121881 · bcb2b86d
  ShihPo Hung authored Apr 08, 2022
  bcb2b86d
Apr 26, 2022
- [RISCV] Pre-commit test for D122769. NFC · 494d86d4
  Craig Topper authored Apr 25, 2022
  
  494d86d4
Apr 25, 2022
- [RISCV] Fix incorrect policy implement for unmasked vslidedown and vslideup. · ffe03ff7
  Zakk Chen authored Apr 25, 2022
  ffe03ff7
Apr 23, 2022
- [RISCV][test] Rename prefix and remove unused text (NFC) · 3a978b7b
  Zakk Chen authored Apr 21, 2022
  3a978b7b
Apr 22, 2022
- [RISCV] Print human-readable VTYPE/SEW/LMUL in MIR · 2b0fedc2
  Fraser Cormack authored Nov 03, 2021
  2b0fedc2
- [RISCV] Update test from SEW to Log2SEW · 9687ca97
  Fraser Cormack authored Apr 22, 2022
  9687ca97
Apr 21, 2022
- [RISCV] Don't emit fractional VIDs with negative steps · 3e678cb7
  Fraser Cormack authored Apr 19, 2022
  3e678cb7
- [RISCV] Add another test showing incorrect BUILD_VECTOR lowering · 627e2104
  Fraser Cormack authored Apr 19, 2022
  627e2104
Apr 19, 2022
- [RISCV] Fix lowering of BUILD_VECTORs as VID sequences · c5cac485
  Fraser Cormack authored Apr 14, 2022
  c5cac485
- [RISCV] Add tests showing incorrect BUILD_VECTOR lowering · 00537946
  Fraser Cormack authored Apr 14, 2022
  00537946
- [RISCV] Add rvv codegen support for vp.fptrunc. · 25445b94
  Jianjian GUAN authored Apr 15, 2022
  25445b94
Apr 15, 2022
- [RISCV][VP] Add RVV codegen for vp.trunc. · 1aa4f0bb
  Jianjian GUAN authored Apr 12, 2022
  1aa4f0bb
Apr 13, 2022
- [RISCV][NFC] Reorganize check prefixes in some tests to reduce redundant lines · 9d2350fd
  Ping Deng authored Apr 13, 2022
  9d2350fd