Commits · 6b76d82853fdc64160dda44610407c04af620292 · Roger Ferrer / llvm-epi · GitLab

Mar 12, 2021
- GlobalISel: Fix marking byval arguments as immutable · 6b76d828
  Matt Arsenault authored Mar 06, 2021
  6b76d828
- GlobalISel: Partially fix handling of byval arguments · 34471c30
  Matt Arsenault authored Mar 05, 2021
  34471c30
- [AMDGPU] Do not annotate an else branch if there is a kill · f08dadd2
  Carl Ritson authored Mar 12, 2021
  f08dadd2
- [AMDGPU] Restrict image_msaa_load to MSAA dimension types · c07f2025
  Carl Ritson authored Mar 12, 2021
  c07f2025
- [AMDGPU] Don't check hasStackObjects() when reserving VGPR · e8e6817d
  Ruiling Song authored Mar 09, 2021
  e8e6817d
Mar 11, 2021
- AMDGPU/GlobalISel: Improve private addressing mode matching · 70cb57d7
  Matt Arsenault authored Mar 04, 2021
  70cb57d7
- GlobalISel: Fix off by one in finding explicit byval alignment · cf5ecd56
  Matt Arsenault authored Mar 06, 2021
  cf5ecd56
- AMDGPU/GlobalISel: Add more tests for byval arguments · 0e0c7ef8
  Matt Arsenault authored Mar 06, 2021
  
  0e0c7ef8
- [AMDGPU] Always create Stack Object for reserved VGPR · 66340846
  Ruiling Song authored Mar 10, 2021
  66340846
- [mir] Change 'undef' for MMO base addresses to 'unknown-address' · 134a179d
  Daniel Sanders authored Mar 05, 2021
  134a179d
Mar 10, 2021
- [AMDGPU] Always expand system scope fp atomics on gfx90a · 574a9dab
  Stanislav Mekhanoshin authored Mar 05, 2021
  574a9dab
- [AMDGPU] Fix isReallyTriviallyReMaterializable for V_MOV_* · 70f013fd
  Jay Foad authored Mar 10, 2021
  70f013fd
- GlobalISel: Try to combine G_[SU]DIV and G_[SU]REM · 4c6ab48f
  Christudasan Devadasan authored Mar 10, 2021
  4c6ab48f
Mar 09, 2021
- [AMDGPU] Fix the dead frame indices during custom spill lowering. · 24c0ad71
  Christudasan Devadasan authored Mar 05, 2021
  24c0ad71
- [AMDGPU] Remove SI_MASK_BRANCH · f0ccdde3
  Ruiling Song authored Feb 25, 2021
  f0ccdde3
Mar 07, 2021
- [SelectionDAG] Add computeKnownBits support for ISD::USUBSAT. · 0eb405c3
  Craig Topper authored Mar 07, 2021
  0eb405c3
Mar 06, 2021
- Revert "Revert "[AMDGPU] Restore the s_memtime instruction in gfx1030"" · 99682bc0
  Jay Foad authored Mar 06, 2021
  99682bc0
- Revert "[AMDGPU] Restore the s_memtime instruction in gfx1030" · e58d68fc
  Mitch Phillips authored Mar 05, 2021
  e58d68fc
Mar 05, 2021
- [AMDGPU] Restore the s_memtime instruction in gfx1030 · fc28f600
  Jay Foad authored Mar 04, 2021
  fc28f600
- [AMDGPU] Do not attempt sgpr spills to vgpr, when it is disabled · 3998a8e7
  RamNalamothu authored Mar 05, 2021
  3998a8e7
- [AMDGPU] Keep skip branch for ds instructions · e0e73714
  Sebastian Neubauer authored Mar 04, 2021
  e0e73714
- Reland AMDGPU/GlobalISel: Combine zext(trunc x) to x after RegBankSelect · 36beaa3b
  Petar Avramovic authored Mar 04, 2021
  36beaa3b
- Reland [GlobalISel] Combine zext(trunc x) to x · d44f61f8
  Petar Avramovic authored Mar 04, 2021
  d44f61f8
Mar 04, 2021
- [AMDGPU] Don't check for VMEM hazards on GFX10 · ed745839
  Jay Foad authored Mar 03, 2021
  ed745839
- Reland [GlobalISel] Start using vectors in GISelKnownBits · d7834556
  Petar Avramovic authored Mar 04, 2021
  d7834556
- [mir] Fix confusing MIR when MMO's value is nullptr but offset is non-zero · 9fc2be6f
  Daniel Sanders authored Mar 02, 2021
  9fc2be6f
- Revert "AMDGPU/GlobalISel: Combine zext(trunc x) to x after RegBankSelect" · e68de60b
  Nico Weber authored Mar 04, 2021
  e68de60b
- Revert "[GlobalISel] Combine zext(trunc x) to x" · 59beb1ef
  Nico Weber authored Mar 04, 2021
  59beb1ef
- Revert "[GlobalISel] Start using vectors in GISelKnownBits" · 4b101536
  Nico Weber authored Mar 04, 2021
  4b101536
- AMDGPU/GlobalISel: Combine zext(trunc x) to x after RegBankSelect · bf5a5826
  Petar Avramovic authored Mar 04, 2021
  bf5a5826
- [GlobalISel] Combine zext(trunc x) to x · 4112299e
  Petar Avramovic authored Mar 04, 2021
  4112299e
- [GlobalISel] Start using vectors in GISelKnownBits · 4c8fb7dd
  Petar Avramovic authored Mar 04, 2021
  4c8fb7dd
Mar 03, 2021
- [VirtRegRewriter] Insert missing killed flags when tracking subregister liveness · 54c0f520
  Baptiste Saleil authored Mar 03, 2021
  54c0f520
- GlobalISel: Add default implementation of assignValueToReg · 78dcff48
  Matt Arsenault authored Mar 02, 2021
  78dcff48
- [AMDGPU] Introduce Strict WQM mode · 4672bac1
  Piotr Sobczak authored Mar 03, 2021
  4672bac1
- [AMDGPU] Rename amdgcn_wwm to amdgcn_strict_wwm · c3ce7bae
  Piotr Sobczak authored Mar 02, 2021
  c3ce7bae
- [AMDGPU] Rename llvm.amdgcn.msaa.load to llvm.amdgcn.msaa.load.x · 2ddac69f
  Carl Ritson authored Mar 03, 2021
  2ddac69f
Mar 02, 2021
- GlobalISel: Merge and cleanup more AMDGPU call lowering code · fd82cbcf
  Matt Arsenault authored Feb 09, 2021
  fd82cbcf
- [AMDGPU][MC][GFX9+] Corrected encoding of op_sel_hi for unused operands in VOP3P · 28f164bc
  Dmitry Preobrazhensky authored Mar 02, 2021
  28f164bc
- [AMDGPU] Do not check max-bb for a single block callee · 7c724a89
  Stanislav Mekhanoshin authored Mar 01, 2021
  7c724a89