Commits · 7116468ca9d0ebec1d97d58d99879eaf7e7a3982 · Roger Ferrer / llvm-epi · GitLab

Jun 08, 2021
- [mlir] fix shared-libs build · 7116468c
  Alex Zinenko authored Jun 08, 2021
  
  7116468c
- [DAG] Allow isNullOrNullSplat to see truncated zeroes · b889c6ee
  David Green authored Jun 08, 2021
  b889c6ee
- [clang] Apply MS ABI details on __builtin_ms_va_list on non-windows platforms on x86_64 · b34da6ff
  Martin Storsjö authored May 31, 2021
  b34da6ff
- [mlir] support memref of memref in standard-to-llvm conversion · c59ce1f6
  Alex Zinenko authored Jun 07, 2021
  c59ce1f6
- [mlir] Make MemRef element type extensible · ada9aa5a
  Alex Zinenko authored Jun 07, 2021
  ada9aa5a
- [mlir] fix integer type mismatch in alloc conversion to LLVM · 3c70a82e
  Alex Zinenko authored Jun 07, 2021
  3c70a82e
- Revert "[mlir][ArmSVE] Add basic mask generation operations" · 57546f5b
  Javier Setoain authored Jun 08, 2021
  57546f5b
- [JITLink] Clarify LinkGraph::splitBlock contract in comment. · 4f16ccda
  Lang Hames authored Jun 05, 2021
  
  4f16ccda
- [lldb] Set return status to failed when adding a command error · e05b03cf
  David Spickett authored Jun 04, 2021
  e05b03cf
- [Demangle][Rust] Parse const backreferences · f9a79356
  Tomasz Miąsko authored Jun 07, 2021
  f9a79356
- [Demangle][Rust] Parse type backreferences · 44d63c57
  Tomasz Miąsko authored Jun 07, 2021
  44d63c57
- [Demangle][Rust] Parse path backreferences · 82b7e822
  Tomasz Miąsko authored Jun 07, 2021
  82b7e822
- [mlir][ArmSVE] Add basic mask generation operations · 392af6a7
  Javier Setoain authored Apr 22, 2021
  392af6a7
- [analyzer] [NFC] Implement a wrapper SValBuilder::getCastedMemRegionVal for... · d3a6181e
  Denys Petrov authored Jun 07, 2021
  d3a6181e
- [Driver] Support libc++ in MSVC · 9625d61e
  Petr Hosek authored Apr 28, 2021
  9625d61e
- [RISCV] Use 0 for Log2SEW for vle1/vse1 intrinsics to enable vsetvli optimization. · 7c4e9a68
  Craig Topper authored Jun 07, 2021
  7c4e9a68
- [RISCV] Masked compares should use a tail agnostic policy. · ae3ab4f0
  Craig Topper authored Jun 07, 2021
  ae3ab4f0
- [RISCV] Use AVL Operand instead of GPR for tied mask pseudo for vwadd.wv and similar. · 7a105b57
  Craig Topper authored Jun 07, 2021
  7a105b57
- BPF: fix relocation types in lib/Object/RelocationResolver.cpp · 8ce45f97
  Yonghong Song authored Jun 07, 2021
  8ce45f97
- [lld-macho] Implement -force_load_swift_libs · 447dfbe0
  Jez Ng authored Jun 07, 2021
  447dfbe0
- [lld-macho] Implement cstring deduplication · 04259cde
  Jez Ng authored Jun 07, 2021
  04259cde
- [yaml2obj] Fix buildbot-issue-4886 · 310d2b49
  Esme-Yi authored Jun 08, 2021
  310d2b49
- [AMDGPU] Allow oversize vaddr in GFX10 MIMG assembly · c8bbfb8c
  Carl Ritson authored Jun 08, 2021
  c8bbfb8c
- [AIX] Define __STDC_NO_ATOMICS__ and __STDC_NO_THREADS__ · f38eff77
  Jake.Egan authored Jun 07, 2021
  f38eff77
- Revert "[AIX] Define __STDC_NO_ATOMICS__ and __STDC_NO_THREADS__ predefined macros" · f97e01e6
  Chris Bowler authored Jun 07, 2021
  f97e01e6
- [AMDGPU] Add v5f32/VReg_160 support for MIMG instructions · f8816c74
  Carl Ritson authored Jun 08, 2021
  f8816c74
- [AIX] Define __STDC_NO_ATOMICS__ and __STDC_NO_THREADS__ predefined macros · e6629be3
  =Jake Egan authored Jun 07, 2021
  e6629be3
- [NFC][scudo] Print errno of fork failure · b41b76b3
  Vitaly Buka authored Jun 07, 2021
  b41b76b3
- [RISCV] Use bitfields to shrink the size of the vector load/store intrinsics... · 0aa94165
  Craig Topper authored Jun 07, 2021
  0aa94165
- [NFC][LSAN] Limit the number of concurrent threads is the test · 11539edf
  Vitaly Buka authored Jun 07, 2021
  11539edf
- [dfsan] Add full fast8 support · 5b4dda55
  George Balatsouras authored Jun 04, 2021
  5b4dda55
- [gn build] Port 692d7166 · 3b69318e
  LLVM GN Syncbot authored Jun 08, 2021
  
  3b69318e
- Revert "[libcxx][gardening] Move all algorithms into their own headers." · 692d7166
  Petr Hosek authored Jun 07, 2021
  692d7166
- Revert "[libcxx][module-map] creates submodules for private headers" · d9633f22
  Petr Hosek authored Jun 07, 2021
  d9633f22
- [RISCV] Optimize bitwise and with constant for the Zbs extension · c705b7b0
  Ben Shi authored Jun 08, 2021
  c705b7b0
- Revert "[TargetLowering] Only inspect attributes in the arguments for ArgListEntry" · 47211fa8
  Arthur Eubanks authored Jun 07, 2021
  47211fa8
- [RISCV] Store Log2 of EEW in the vector load/store intrinsic to pseudo lookup tables. NFCI · 9b92ae01
  Craig Topper authored Jun 07, 2021
  9b92ae01
- [AMDGPU] Handle constant LDS uses from different kernels · 05289dfb
  Stanislav Mekhanoshin authored Jun 07, 2021
  05289dfb
- [AMDGPU] Introduce command line switch to control super aligning of LDS. · 713ca2f3
  hsmahesha authored Jun 08, 2021
  713ca2f3
Jun 07, 2021
- [IR] Add utility to convert constant expression operands (of an instruction) to instructions. · 3af5f3e6
  hsmahesha authored Jun 08, 2021
  3af5f3e6