- Aug 09, 2018
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Reid Kleckner authored
The inalloca parameter has to be the only parameter passed in memory. Changing the convention to fastcc can break that. At some point we should teach global opt how to optimize ABI attributes like inalloca and maybe byval. These attributes are mainly used to match C ABIs. They are harder for LLVM to optimize and they don't always generate the best code. Fixes PR38487 llvm-svn: 339360
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Sanjay Patel authored
Similar to rL337966 - if the DAGCombiner's rotate matching was working as expected, I don't think we'd see any test diffs here. AArch only goes right, and PPC only goes left. x86 has both, so no diffs there. Differential Revision: https://reviews.llvm.org/D50091 llvm-svn: 339359
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Paul Semel authored
Differential Revision: https://reviews.llvm.org/D49979 llvm-svn: 339358
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Michael Berg authored
Summary: This change provides a common optimization path for both Unsafe and FMF driven optimization for this fsub fold adding reassociation, as it the flag that most closely represents the translation Reviewers: spatel, wristow, arsenm Reviewed By: spatel Subscribers: wdng Differential Revision: https://reviews.llvm.org/D50195 llvm-svn: 339357
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Evandro Menezes authored
Enable `FeatureZCZeroing`, `FeatureHasSlowFPVMLx`, `FeatureExpandMLx`, `FeatureProfUnpredicate`, `FeatureSlowVDUP32`, `FeatureSlowVGETLNi32`, `FeatureSplatVFPToNeon`, `FeatureHasRetAddrStack`, `FeatureSlowFPBrcc` for all Exynos processors. llvm-svn: 339356
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Evandro Menezes authored
Add new feature, `FeatureUseWideStrideVFP`, that replaces the need for a processor check. Otherwise, NFC. llvm-svn: 339354
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Raphael Isemann authored
llvm-svn: 339353
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Andrea Di Biagio authored
This patch introduces tablegen class MCStatement. Currently, an MCStatement can be either a return statement, or a switch statement. ``` MCStatement: MCReturnStatement MCOpcodeSwitchStatement ``` A MCReturnStatement expands to a return statement, and the boolean expression associated with the return statement is described by a MCInstPredicate. An MCOpcodeSwitchStatement is a switch statement where the condition is a check on the machine opcode. It allows the definition of multiple checks, as well as a default case. More details on the grammar implemented by these two new constructs can be found in the diff for TargetInstrPredicates.td. This patch makes it easier to read the body of auto-generated TargetInstrInfo predicates. In future, I plan to reuse/extend the MCStatement grammar to describe more complex target hooks. For now, this is just a first step (mostly a minor cosmetic change to polish the new predicates framework). Differential Revision: https://reviews.llvm.org/D50457 llvm-svn: 339352
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Raphael Isemann authored
Summary: Instead of just printing the current "False is not True, ..." message when we fail to run a certain command, this patch also adds the actual command output or error output that we received to the assertion message. Reviewers: davide Reviewed By: davide Subscribers: lldb-commits Differential Revision: https://reviews.llvm.org/D50492 llvm-svn: 339351
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Bjorn Pettersson authored
Summary: The interface to get size and spill size of a register was moved from MCRegisterInfo to TargetRegisterInfo over a year ago. Afaik the old interface has bee around to give out-of-tree targets a chance to adapt to the new interface. One problem with the old MCRegisterClass::PhysRegSize was that it represented the size of a register as "size in bits" / 8. So a register had to be a multiple of eight bits wide for the size to be correct (and the byte size for the target needed to be eight bits). Reviewers: kparzysz, qcolombet Reviewed By: kparzysz Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D47199 llvm-svn: 339350
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Sanjay Patel authored
llvm-svn: 339349
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George Rimar authored
It covers the following line with a test: https://github.com/llvm-mirror/lld/blob/master/ELF/OutputSections.cpp#L383 llvm-svn: 339348
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Sjoerd Meijer authored
Differential Revision: https://reviews.llvm.org/D50175 llvm-svn: 339347
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Simon Pilgrim authored
As requested in D50392, pull the magic constant calculations out into a helper function. llvm-svn: 339346
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Hans Wennborg authored
link.exe ignores REL32 relocations on 32-bit x86, as well as relocations against non-function symbols such as labels. This makes lld do the same. Differential Revision: https://reviews.llvm.org/D50430 llvm-svn: 339345
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Erich Keane authored
As a part of attempting to clean up the way attributes are printed, this patch adds an operator << to the diagnostics/ partialdiagnostics so that ParsedAttr can be sent directly. This patch also rewrites a large amount* of the times when ParsedAttr was printed using its IdentifierInfo object instead of being printed itself. *"a large amount" == "All I could find". llvm-svn: 339344
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Tim Northover authored
This test relies on communicating with debugserver via an unnamed (pre-opened) pipe, but macOS's version of debugserver doesn't seem to support that mode of operation. So disable the test for now. llvm-svn: 339343
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George Rimar authored
This adds a test for https://github.com/llvm-mirror/lld/blob/master/ELF/ScriptParser.cpp#L1289. llvm-svn: 339342
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Sjoerd Meijer authored
Differential Revision: https://reviews.llvm.org/D50454 llvm-svn: 339340
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Simon Pilgrim authored
Exposed by D50328 Differential Revision: https://reviews.llvm.org/D50328 llvm-svn: 339337
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Gabor Marton authored
Summary: Currently we consider one forward declared RecordDecl and another with a definition equal. We have to do the same in case of enums. Reviewers: a_sidorin, r.stahl, xazax.hun Subscribers: rnkovacs, dkrupp, cfe-commits Differential Revision: https://reviews.llvm.org/D50444 llvm-svn: 339336
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Simon Pilgrim authored
As discussed on D41794, we have many cases where we fail to combine shuffles as the input operands have other uses. This patch permits these shuffles to be combined as long as they don't introduce additional variable shuffle masks, which should reduce instruction dependencies and allow the total number of shuffles to still drop without increasing the constant pool. However, this may mean that some memory folds may no longer occur, and on pre-AVX require the occasional extra register move. This also exposes some poor PMULDQ/PMULUDQ codegen which was doing unnecessary upper/lower calculations which will in fact fold to zero/undef - the fix will be added in a followup commit. Differential Revision: https://reviews.llvm.org/D50328 llvm-svn: 339335
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Gabor Marton authored
Reviewers: a_sidorin, r.stahl, xazax.hun Subscribers: rnkovacs, dkrupp, cfe-commits Differential Revision: https://reviews.llvm.org/D50428 llvm-svn: 339334
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George Rimar authored
This covers the following line: https://github.com/llvm-mirror/lld/blob/master/ELF/ScriptParser.cpp#L415 llvm-svn: 339333
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Sid Manning authored
This is a larger patch. This relocation has irregular immediate masks that require a lookup to find the correct mask. Differential Revision: https://reviews.llvm.org/D50450 llvm-svn: 339332
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Hans Wennborg authored
llvm-svn: 339330
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Hans Wennborg authored
It previously erroneously said only VS2015 was required. llvm-svn: 339329
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Tatyana Krasnukha authored
llvm-svn: 339328
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George Rimar authored
This covers the following line with a test: https://github.com/llvm-mirror/lld/blob/master/ELF/ScriptParser.cpp#L415 llvm-svn: 339327
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George Rimar authored
This adds a coverage for the following line of the code: https://github.com/llvm-mirror/lld/blob/master/ELF/ScriptParser.cpp#L274 llvm-svn: 339326
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Eric Liu authored
http://lab.llvm.org:8011/builders/clang-cmake-armv8-quick/builds/5487 llvm-svn: 339322
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Andrew V. Tischenko authored
Differential Revision: https://reviews.llvm.org/D49861 llvm-svn: 339321
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Eric Liu authored
Summary: This allows implementations like different symbol indexes to know what the current active file is. For example, some customized index implementation might decide to only return results for some files. Reviewers: ilya-biryukov Reviewed By: ilya-biryukov Subscribers: javed.absar, MaskRay, jkorous, arphaman, cfe-commits Differential Revision: https://reviews.llvm.org/D50446 llvm-svn: 339320
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Hans Wennborg authored
llvm-svn: 339319
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David Carlier authored
As for Linux with its getrandom's syscall, giving the possibility to fill buffer with native call for good quality but falling back to /dev/urandom in worst case similarly. Reviewers: vitalybuka, krytarowski Reviewed By: vitalybuka Differential Revision: https://reviews.llvm.org/D48804 llvm-svn: 339318
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David Chisnall authored
Summary: Windows does not allow globals to be initialised to point to globals in another DLL. Exported globals may be referenced only from code. Work around this by creating an initialiser that runs in early library initialisation and sets the isa pointer. Reviewers: rjmccall Reviewed By: rjmccall Subscribers: cfe-commits Differential Revision: https://reviews.llvm.org/D50436 llvm-svn: 339317
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Jonas Hahnfeld authored
According to PTX ISA .volatile has the same memory synchronization semantics as .relaxed.sys, so it can be used to implement monotonic atomic loads and stores. This is important for OpenMP's atomic construct where - 'read's and 'write's are lowered to atomic loads and stores, and - an update of float or double types are lowered into a cmpxchg loop. (Note that PTX could do better because it has atom.add.f{32,64} but LLVM's atomicrmw instruction only allows integer types.) Higher levels of atomicity (like acquire and release) need additional synchronization properties which were added with PTX ISA 6.0 / sm_70. So using these instructions still results in an error. Differential Revision: https://reviews.llvm.org/D50391 llvm-svn: 339316
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Roger Ferrer Ibanez authored
This pseudo-instruction is similar to la but uses PC-relative addressing unconditionally. This is, la is only different to lla when using -fPIC. This pseudo-instruction seems often forgotten in several specs but it is definitely mentioned in binutils opcodes/riscv-opc.c. The semantics are defined both in page 37 of the "RISC-V Reader" book but also in function macro found in gas/config/tc-riscv.c. This is a very first step towards adding PIC support for Linux in the RISC-V backend. The lla pseudo-instruction expands to a sequence of auipc + addi with a couple of pc-rel relocations where the second points to the first one. This is described in https://github.com/riscv/riscv-elf-psabi-doc/blob/master/riscv-elf.md#pc-relative-symbol-addresses For now, this patch only introduces support of that pseudo instruction at the assembler parser. Differential Revision: https://reviews.llvm.org/D49661 llvm-svn: 339314
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Tobias Grosser authored
We upstreamed the export of isl_val_2exp, to the official cpp bindings. In this process, we concluded that pow2 is a better and more widely used name for this functionality. Hence, both the official isl-cpp bindings and our derived variant use now the term pow2. llvm-svn: 339312
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Tobias Grosser authored
This update fixes https://https:/llvm.org/PR38348. Thanks Michael for reporting the issue to isl and Sven for fixing the issue. llvm-svn: 339311
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