Patch by Dave Huseby.

llvm-svn: 230669

The shadow stack space expectations won't match.

Fixes PR22709.

llvm-svn: 230667

llvm-svn: 230664

InstCombine has long had logic to convert aligned Altivec load/store intrinsics
into regular loads and stores. This mirrors that functionality for QPX vector
load/store intrinsics.

llvm-svn: 230660

have the debugger step through each one individually. Turn off the
combine for adjacent stores at -O0 so we get this behavior.

Possibly, DAGCombine shouldn't run at all at -O0, but that's for
another day; see PR22346.

Differential Revision: http://reviews.llvm.org/D7181

llvm-svn: 230659

llvm-svn: 230658

There was a problem when passing structures as variable arguments.
The structures smaller than 64 bit were not left justified on MIPS64
big endian. This is now fixed by shifting the value to make it left-
justified when appropriate.

This fixes the bug http://llvm.org/bugs/show_bug.cgi?id=21608

Patch by Aleksandar Beserminji.

Differential Revision: http://reviews.llvm.org/D7881

llvm-svn: 230657

The gold plugin never calls MaterializeModule, so any old debug info
was not deleted and could cause crashes.

Now that it is being "upgraded", the plugin also has to handle warnings
and create Modules with a nice id (it shows in the warning).

llvm-svn: 230655

In case of "krait" CPU, asm printer doesn't emit any ".cpu" so the
features bits are not computed. This patch lets the asm printer
emit ".cpu cortex-a9" directive for krait and the hwdiv feature is
enabled through ".arch_extension". In short, krait is treated
as "cortex-a9" with hwdiv. We can not emit ".krait" as CPU since
it is not supported bu GNU GAS yet

llvm-svn: 230651

This patch is in response to r223147 where the avaiable features are
computed based on ".cpu" directive. This will work clean for the standard
variants like cortex-a9. For custom variants which rely on standard cpu names
for assembly, the additional features of a CPU should be propagated. This can be
done via ".arch_extension" as long as the assembler supports it. The
implementation for krait along with unit test will be submitted in next patch.

llvm-svn: 230650

accesses are via different types

Noticed this while generalizing the code for loop distribution.

I confirmed with Arnold that this was indeed a bug and managed to create
a testcase.

llvm-svn: 230647

This matches the assembly syntax for the proprietary compiler.

llvm-svn: 230645

llvm-svn: 230638

Turns out that after the past MMX commits, we don't need to rely on this
flag to get better codegen for MMX. Also update the tests to become
triple neutral.

llvm-svn: 230637

The latency for the WriteMULm class was set to 4, which is actually lower than the latency for WriteMULr (5). 
A better estimate would be 4 added to WriteMULr, that is, 9.

llvm-svn: 230634

InstCombine has logic to convert aligned Altivec load/store intrinsics into
regular loads and stores. Unfortunately, there seems to be no regression test
covering this behavior. Adding one...

llvm-svn: 230632

llvm-svn: 230628

formulaic into the top v8i16 lowering routine.

This makes the generalized lowering a completely general and single path
lowering which will allow generalizing it in turn for multiple 128-bit
lanes.

llvm-svn: 230623

MVT.

llvm-svn: 230622

backedge-taken count in profiliing data.

llvm-svn: 230619

IRCE can now split the iteration space for loops like:

   for (i = n; i >= 0; i--)
     a[i + k] = 42; // bounds check on access

llvm-svn: 230618

This ordering matches that of DAG.getNode.

llvm-svn: 230617

Apparently we can use this now!

llvm-svn: 230613

Add `CHECK-SAME`, which requires that the pattern matches on the *same*
line as the previous `CHECK`/`CHECK-NEXT` -- in other words, no newline
is allowed in the skipped region.  This is similar to `CHECK-NEXT`,
which requires exactly 1 newline in the skipped region.

My motivation is to simplify checking the long lines of LLVM assembly
for the new debug info hierarchy.  This allows CHECK sequences like the
following:

    CHECK:      ![[REF]] = !SomeMDNode(
    CHECK-SAME: file: ![[FILE:[0-9]+]]
    CHECK-SAME: otherField: 93{{[,)]}}

which is equivalent to:

    CHECK: ![[REF]] = !SomeMDNode({{.*}}file: ![[FILE:[0-9]+]]{{.*}}otherField: 93{{[,)]}}

While this example just has two fields, many nodes in debug info have
more than that.  `CHECK-SAME` will keep the logic easy to follow.

Morever, it enables interleaving `CHECK-NOT`s without allowing newlines.
Consider the following:

    CHECK:      ![[REF]] = !SomeMDNode(
    CHECK-SAME: file: ![[FILE:[0-9]+]]
    CHECK-NOT:  unexpectedField:
    CHECK-SAME: otherField: 93{{[,)]}}
    CHECK-NOT:  otherUnexpectedField:
    CHECK-SAME: )

which doesn't seem to have an equivalent `CHECK` line.

llvm-svn: 230612

Add a default constructor for `DIImportedEntity`, to be used in clang in
a follow-up.

llvm-svn: 230609

Also remove the somewhat misleading initializers from
VectorizationFactor and VectorizationInterleave.  They will get
initialized with the default ctor since no cl::init is provided.

llvm-svn: 230608

llvm-svn: 230607

When I originally committed the statepoint docs, I left placeholders for example IR fragments.  I'm finally getting around to filling those in.  

I also added IR fragments to illustrate the usage of the PlaceSafepoints pass while I was at it.

llvm-svn: 230601

llvm-svn: 230599

It still prints "Assembling path/to/X86CompilationCallback_Win64.asm",
but linking does the same thing.

llvm-svn: 230596

Use the IRBuilder helpers for gc.statepoint and gc.result, instead of
coding the construction by hand. Note that the gc.statepoint IRBuilder
handles only CallInst, not InvokeInst; retain that part of hand-coding.

Differential Revision: http://reviews.llvm.org/D7518

llvm-svn: 230591

Explanation: This function is in TargetLowering because it uses
RegClassForVT which would need to be moved to TargetRegisterInfo
and would necessitate moving isTypeLegal over as well - a massive
change that would just require TargetLowering having a TargetRegisterInfo
class member that it would use.

llvm-svn: 230585

llvm-svn: 230584

This required plumbing a TargetRegisterInfo through computeRegisterProperties
and into findRepresentativeClass which uses it for register class
iteration. This required passing a subtarget into a few target specific
initializations of TargetLowering.

llvm-svn: 230583

Differential Revision: http://reviews.llvm.org/D7644

llvm-svn: 230582

llvm-svn: 230581

Add a brief section linking to the experimental statepoint intrinsics analogous to the one we have linking to patchpoint.  

While I'm here, cleanup some wording about what the gc "name" attribute actually means.  It's not the name of a *collector* it's the name of the *strategy* which may be compatible with multiple collectors.

llvm-svn: 230576

llvm-svn: 230572

llvm-svn: 230570

This particular subtype of Mach-O was missing. Add it.

llvm-svn: 230567