Commits · 9b809cc5b69a45601910bf4c60a2ece2f5462a18 · Roger Ferrer / llvm-epi · GitLab

Oct 21, 2022
- [LLDB][NativePDB] Improve ParseDeclsForContext time. · 9b809cc5
  Zequan Wu authored Oct 14, 2022
  9b809cc5
- [InstCombine] allow more commutative matches for logical-and to select fold · 30730745
  Sanjay Patel authored Oct 21, 2022
  30730745
- Let MLIR ODS also support generating build() functions without result type... · 7dd2f4bc
  Zhixun Tan authored Oct 21, 2022
  7dd2f4bc
- [mlir][index] Fix NoSideEffect->Pure · 878d5414
  Jeff Niu authored Oct 21, 2022
  
  878d5414
- [mlir][index] Add `convert-index-to-llvm` pass · cae746d9
  Jeff Niu authored Oct 11, 2022
  cae746d9
- [mlir][index] Add folders for `index` ops · 83c3eebd
  Jeff Niu authored Oct 11, 2022
  83c3eebd
- [mlir][index] Add `index` dialect ops and attributes · ddf87d6c
  Jeff Niu authored Oct 11, 2022
  ddf87d6c
- [mlir][index] Add boilerplate for the `index` dialect · 8bef3541
  Jeff Niu authored Oct 10, 2022
  8bef3541
- [ELF] Suppress "duplicate symbol" when resolving STB_WEAK and STB_GNU_UNIQUE in different COMDATs · 0051b6bb
  Fangrui Song authored Oct 21, 2022
  0051b6bb
- [PGO][AIX] Improve dummy var retention and allow -bcdtors:csect linking. · 461a1836
  Wael Yehia authored Oct 20, 2022
  461a1836
- [AArch64][SVE2] Add the SVE2.1 fdot instructions · 4fd2b491
  David Sherwood authored Oct 19, 2022
  4fd2b491
- [libc++][NFC] Add documentation for _Or and _And · fc41512f
  Louis Dionne authored Oct 21, 2022
  
  fc41512f
- [mlir][scf] Add an IndexSwitchOp · 07d8fe93
  Jeff Niu authored Oct 16, 2022
  07d8fe93
- [llvm-reduce] Attempt to strip debug info · 0fbb2615
  Arthur Eubanks authored Oct 18, 2022
  0fbb2615
- [RISCV] Add missing vscale x 1 cost model entries and tests. · 02045021
  Craig Topper authored Oct 21, 2022
  02045021
- [AMDGPU] Use VGPR classes in divergent build_vector patterns · 31bd3e6e
  Jay Foad authored Oct 21, 2022
  31bd3e6e
- [mlir][sparse] Refactor the convert operator conversion to support codegen for the operator. · b056d0bb
  bixia1 authored Oct 21, 2022
  b056d0bb
- [MachineVerifier] Try harder to verify LiveVariables · d4650d09
  Jay Foad authored Jul 06, 2022
  d4650d09
- [InstCombine] allow some commutative matches for logical-and to select fold · d7fecf26
  Sanjay Patel authored Oct 21, 2022
  d7fecf26
- [InstCombine] refactor matching code for logical ands; NFCI · f6fc3e23
  Sanjay Patel authored Oct 21, 2022
  f6fc3e23
- [flang] Fix FIRSupport build race condition with HLFIRDialect · 2c0d0566
  Jean Perier authored Oct 21, 2022
  2c0d0566
- [test] Use -passes in more Transforms tests · 211cf8a3
  Bjorn Pettersson authored Oct 21, 2022
  211cf8a3
- [instcombine] Add basic test coverage for demanded bits of scalable vectors · 656e53e5
  Philip Reames authored Oct 21, 2022
  
  656e53e5
- [AArch64]SME2 Multi-vector-Multiple Vectors SQDMULH instructions · d3c8aa7a
  Caroline Concatto authored Oct 20, 2022
  d3c8aa7a
- [AArch64][SVE2] Add the SVE2.1 fclamp instructions · d78c3b32
  David Sherwood authored Oct 19, 2022
  d78c3b32
- [NFC] Make sure we check an optional when checking function constraints · a726be38
  Erich Keane authored Oct 21, 2022
  a726be38
- [LLVMIR] Use helper methods to set/check readnone attribute (NFC) · 87549e61
  Nikita Popov authored Oct 21, 2022
  87549e61
- [AAArch64][Windows] Fix the crash when running ninja check-asan · ec4db1d0
  chenglin.bi authored Oct 21, 2022
  ec4db1d0
- [AArch64] Add SVE2.1 target feature for Armv9-A 2022 Architecture Extension · fcd54586
  David Sherwood authored Oct 18, 2022
  fcd54586
- [TwoAddressInstruction] Fix stale LiveVariables info in processStatepoint · 33f78d09
  Jay Foad authored Oct 21, 2022
  33f78d09
- [AArch64] SME2 Multiple vectors int/float binary accumulator and two/four ZA single-vector · 3bee2fb2
  Caroline Concatto authored Oct 21, 2022
  3bee2fb2
- [mlir][linalg] Add one-shot-bufferize tests for Linalg ops: reduce, map and transpose. · 00ac3957
  Oleg Shyshkov authored Oct 21, 2022
  00ac3957
- [AArch64]SME2 multi-vec FP/INT down convert 2/4 registers · 830b5e82
  Caroline Concatto authored Oct 20, 2022
  830b5e82
- [AArch64]SME2 Multi-vector - Index/Single/Multi Array Vectors FMA sources · fc0cde8a
  Caroline Concatto authored Oct 20, 2022
  fc0cde8a
- [X86] Fix typo of mtamx_int8 · 3770d2b9
  Luo, Yuanke authored Oct 21, 2022
  
  3770d2b9
- [clangd] Add highlighting modifier "constructorOrDestructor" · 8b366875
  Christian Kandeler authored Aug 04, 2022
  8b366875
- [CostModel][X86] Remove duplicate RUN line from cttz cost tests · ca5fbac7
  Simon Pilgrim authored Oct 21, 2022
  
  ca5fbac7
- [InstCombine] match logical and/or more generally in fold to select · bf75e937
  Sanjay Patel authored Oct 21, 2022
  bf75e937
- [InstCombine] add tests for logical selects; NFC · 5a53fe84
  Sanjay Patel authored Oct 20, 2022
  
  5a53fe84
- [AArch64]SME2 Multi-single vector SVE Destructive 2 and 4 Registers · 1e4f82c2
  Caroline Concatto authored Oct 17, 2022
  1e4f82c2