Commits · 9e7febb4f73c8584f622d4dad17be5417938eb10 · Roger Ferrer / llvm-epi · GitLab

Nov 22, 2022
- [AMDGPU][GISel] Select llvm.amdgcn.fcmp intrinsics · 9e7febb4
  Pierre van Houtryve authored Nov 22, 2022
  9e7febb4
- [SelectOptimize] Add some debug logging. NFC · 7d098988
  David Green authored Nov 22, 2022
  7d098988
- [RISCV][NFC] Mark rs1 in most memory instructions as memory operand. · 95ef0052
  Dmitry Bushev authored Nov 22, 2022
  95ef0052
- [InstCombine] Fold extractelt with select of constants · 470aea5e
  Thomas Symalla authored Nov 14, 2022
  470aea5e
- Revert "[CodeGen] Use poison instead of undef as placeholder in AtomicExpandPass [NFC]" · b50e1bd6
  Nuno Lopes authored Nov 22, 2022
  b50e1bd6
- [XCOFF] set fragment for XMC_PR csects. · c7c7ef8b
  esmeyi authored Nov 22, 2022
  c7c7ef8b
- [CodeGen] Use poison instead of undef as placeholder in AtomicExpandPass [NFC] · f50423c1
  Manuel Brito authored Nov 22, 2022
  f50423c1
- [CodeGen] Refactor visitSCALAR_TO_VECTOR. NFC. · caa9f630
  Han-Kuan Chen authored Nov 08, 2022
  caa9f630
- [RISCV] Add CodeGen support and MC testcase of RISCV Zca Extension · 219417b2
  WuXinlong authored Nov 21, 2022
  219417b2
- [AMDGPU] Make aperture registers 64 bit · 220147d5
  Pierre van Houtryve authored Nov 22, 2022
  220147d5
- [SCEV][NFC] Introduce API for getting basic block's symbolic max exit count · f285be62
  Max Kazantsev authored Nov 22, 2022
  f285be62
- [SCEV][NFC] Call getExitCount with SymbolicMaximum when computing loop symbolic max · b803957b
  Max Kazantsev authored Nov 22, 2022
  b803957b
- [AMDGPU][GISel] Add llvm.amdgcn.icmp selection · a751676f
  Pierre van Houtryve authored Nov 22, 2022
  a751676f
- [PowerPC][GISel]add support for float point arithmetic operations · d9143ce3
  Chen Zheng authored Nov 22, 2022
  d9143ce3
- [LoongArch] Support when the depth of __builtin_frame_address is greater than zero · 801c77bb
  gonglingqin authored Nov 22, 2022
  801c77bb
- [PowerPC] store the LR before stack update for big offsets. · 375323fb
  Chen Zheng authored Nov 22, 2022
  375323fb
- [LoopFlatten] Fix IV increment use count · 8e9e22f0
  David Green authored Nov 22, 2022
  8e9e22f0
- [IndVarSimplify] Lift limitations on IV being a Phi for turn-to-invariant · 57fd7ffe
  Max Kazantsev authored Nov 22, 2022
  57fd7ffe
- [RISCV] Remove SExtWRemovalCands set from RISCVSExtWRemoval. · f99514ac
  Craig Topper authored Nov 21, 2022
  f99514ac
- [RISCV] Transform fixable instruction in place in RISCVSExtWRemoval. NFC · 4e6adb39
  Craig Topper authored Nov 21, 2022
  4e6adb39
- [RISCV] Prevent constant hoisting for (and (shl X, C), mask<<C) · a391b49c
  Craig Topper authored Nov 21, 2022
  a391b49c
- Return None instead of Optional<T>() (NFC) · 6ba4b62a
  Kazu Hirata authored Nov 21, 2022
  6ba4b62a
- Don't use Optional::getPointer (NFC) · 1f914944
  Kazu Hirata authored Nov 21, 2022
  1f914944
- [X86] Allow no X87 on 32-bit · b39b76f2
  Phoebe Wang authored Nov 22, 2022
  b39b76f2
- [AArch64] Remove emitCalleeSavedFrameMoves · 90d78170
  Kazu Hirata authored Nov 21, 2022
  90d78170
- [PowerPC] Add support for G_ADD and G_SUB. · 2b1e895a
  Kai Nacke authored Nov 21, 2022
  2b1e895a
Nov 21, 2022
- [WebAssembly] Disable register coalescing at -O1 · d9ae0788
  Heejin Ahn authored Nov 15, 2022
  d9ae0788
- [SCEV] Iteratively compute ranges for deeply nested expressions. · 5dad4c67
  Florian Hahn authored Nov 21, 2022
  5dad4c67
- [PowerPC] Move PPCGenRegisterBankInfo.def into the directory where it would be... · a617ff0b
  Benjamin Kramer authored Nov 21, 2022
  a617ff0b
- Restore global descriptor demangling after D138095 "[asan] Keep Itanium... · db7c8223
  Fangrui Song authored Nov 21, 2022
  db7c8223
- [WebAssembly] Update relaxed-simd instruction names · ae96b5bd
  Thomas Lively authored Nov 21, 2022
  ae96b5bd
- [PowerPC] Extend GlobalISel implementation to emit and/or/xor. · be4a1dfb
  Kai Nacke authored Sep 16, 2022
  be4a1dfb
- [PowerPC] Add new load/store with length instructions to Future CPU. · bd680704
  Maryam Moghadas authored Oct 28, 2022
  bd680704
- [Passes][VectorCombine] enable early run generally and try load folds · 163bb6d6
  Sanjay Patel authored Nov 21, 2022
  163bb6d6
- [VectorCombine] generalize pass param name for early combines; NFC · 8f337f8f
  Sanjay Patel authored Nov 19, 2022
  8f337f8f
- Use poison instead of undef as placeholder for vector construction [NFC] · 1e55d5b1
  Manuel Brito authored Nov 21, 2022
  1e55d5b1
- [Support] Reduce Dependence on Host.h · 53d234ea
  Archibald Elliott authored Nov 21, 2022
  53d234ea
- [SLP]Fix PR59098: check if the vector type is scalarized for · ac93b611
  Alexey Bataev authored Nov 21, 2022
  ac93b611
- [AArch64][SME]: Generate streaming-compatible code for fp_to_int and int_to_fp. · 70180ee0
  Hassnaa Hamdi authored Nov 18, 2022
  70180ee0
- [RISCV] Add isel patterns to select slli+shXadd.uw. · 24810acb
  Craig Topper authored Nov 21, 2022
  24810acb