Commits · b5ef56f0bc9b51bd026a643d4a541af9993aaf89 · Roger Ferrer / llvm-epi · GitLab

Nov 07, 2021
- [X86][AVX] Add missing X86ISD::VBROADCAST(v4f32 -> v8f32) isel pattern for AVX1 targets · b5ef56f0
  Simon Pilgrim authored Nov 07, 2021
  b5ef56f0
- [X86] Add AVX512 test coverage to vselect-zero.ll · f7880a78
  Simon Pilgrim authored Nov 07, 2021
  f7880a78
Nov 05, 2021
- [TwoAddressInstructionPass] Update existing physreg live intervals · bdaa1810
  Jay Foad authored Nov 04, 2021
  bdaa1810
- [DAGCombiner] add fold for vselect based on mask of signbit, part 2 · 7e30404c
  Sanjay Patel authored Nov 05, 2021
  7e30404c
- [AArch] add tests for vselect; NFC · 4d513f25
  Sanjay Patel authored Nov 05, 2021
  4d513f25
- [x86] add tests for vector select; NFC · fc852462
  Sanjay Patel authored Nov 05, 2021
  
  fc852462
- [AArch64][GISel] Optimize 8 and 16 bit variants of uaddo. · f64580f8
  Florian Hahn authored Nov 05, 2021
  f64580f8
- [RISCV] Support Zfhmin extension · 5c3d7184
  Shao-Ce SUN authored Nov 06, 2021
  5c3d7184
- [RISCV] Enable FP extensions and ABI on fixed-vectors-bitcast.ll. · 085accea
  Craig Topper authored Nov 04, 2021
  085accea
- [DAGCombiner] add fold for vselect based on mask of signbit · 4fc1fc40
  Sanjay Patel authored Nov 05, 2021
  4fc1fc40
- [AArch64] add tests for vector select; NFC · 1e7afa2a
  Sanjay Patel authored Nov 04, 2021
  
  1e7afa2a
- [x86] add tests for vector select; NFC · 89188140
  Sanjay Patel authored Nov 04, 2021
  
  89188140
- [AArch64] Add target DAG combine for UUNPKHI/LO · 657a1dcd
  David Sherwood authored Nov 04, 2021
  657a1dcd
- [AArch64] Fix a bug from a pattern for uaddv(uaddlp(x)) ==> uaddlv · a7b18725
  Jingu Kang authored Nov 05, 2021
  a7b18725
- [FreeBSD] Do not mark __stack_chk_guard as dso_local · 1cb9f37a
  Alfredo Dal'Ava Junior authored Nov 05, 2021
  1cb9f37a
- [DAG] FoldConstantArithmetic - fold bitlogic(bitcast(x),bitcast(y)) -> bitcast(bitlogic(x,y)) · c1e7911c
  Simon Pilgrim authored Nov 05, 2021
  c1e7911c
- [X86] Enable v32i16 rotate lowering on non-BWI targets · 5e9ac7c0
  Simon Pilgrim authored Nov 05, 2021
  5e9ac7c0
- [ARM] Extra MVE constant select test. NFC · cb62c376
  David Green authored Nov 05, 2021
  
  cb62c376
- [PowerPC] use correct selection for v16i8/v8i16 splat load · fed2889f
  Chen Zheng authored Nov 05, 2021
  fed2889f
- Revert "[TwoAddressInstructionPass] Update existing physreg live intervals" · 0321bd64
  Jay Foad authored Nov 05, 2021
  0321bd64
- [TwoAddressInstructionPass] Update existing physreg live intervals · ec0e1e88
  Jay Foad authored Nov 04, 2021
  ec0e1e88
- [PowerPC] Add intrinsic to convert between ppc_fp128 and fp128 · 5fd406e2
  Qiu Chaofan authored Nov 05, 2021
  5fd406e2
- [X86][MS-InlineAsm][test] Add triple in ms-inline-asm-array.ll · 6d03227c
  Shengchen Kan authored Nov 05, 2021
  6d03227c
- [X86][MS-InlineAsm] Add constraint *m for memory access w/ global var · be08e452
  Shengchen Kan authored Nov 03, 2021
  be08e452
- BPF: Support btf_type_tag attribute · 41860e60
  Yonghong Song authored Oct 17, 2021
  41860e60
Nov 04, 2021
- [AMDGPU] Changes the AMDGPU_Gfx calling convention by making the SGPRs 4..29... · 76cbe622
  Thomas Symalla authored Oct 25, 2021
  76cbe622
- [X86][SSE] Regenerate vector funnel shift tests · fe75d0c3
  Simon Pilgrim authored Nov 04, 2021
  
  fe75d0c3
- [ARM] Move VPTBlock pass after post-ra scheduling · 09124402
  David Green authored Nov 04, 2021
  09124402
- [RISCV] Add another test case showing unnecessary vsetvli near mask instructions. · f1b79915
  Craig Topper authored Nov 04, 2021
  f1b79915
- [RISCV] Rename some assembler mnemonic and intrinsic functions for RVV 1.0. · 0649dfeb
  Zakk Chen authored Nov 04, 2021
  0649dfeb
- [ARM] Regenerate shift-combine.ll test checks · a763d001
  Simon Pilgrim authored Nov 04, 2021
  
  a763d001
- [AMDGPU] Regenerate shift-and-i128-ubfe.ll test checks · 53becf5d
  Simon Pilgrim authored Nov 04, 2021
  
  53becf5d
- [X86][SSE] Improve PMADDWD SimplifyDemandedVectorElts handling · 87d5bb66
  Simon Pilgrim authored Nov 04, 2021
  87d5bb66
- [PowerPC] Enforce side effects to FPSCR read/set intrinsics · a8411875
  Qiu Chaofan authored Nov 04, 2021
  a8411875
- [AMDGPU] Do not add debug locations to the code inside prologue · 539f500e
  RamNalamothu authored Nov 03, 2021
  539f500e
Nov 03, 2021
- X86InstrInfo: Support immediates that are +1/-1 different in optimizeCompareInstr · 847a6807
  Matthias Braun authored Sep 27, 2021
  847a6807
- [AMDGPU] Enable divergence-driven BFE selection · 0a3d755e
  alex-t authored Oct 31, 2021
  0a3d755e
- [X86] Fix X32 indirect call generation · 889c2b97
  Harald van Dijk authored Nov 03, 2021
  889c2b97
- Revert "X86InstrInfo: Support immediates that are +1/-1 different in optimizeCompareInstr" · a2a58d91
  Hans Wennborg authored Nov 03, 2021
  a2a58d91
- [NVPTX] Mark special registers as reserved · 123ad720
  Andrew Savonichev authored Nov 03, 2021
  123ad720