Commits · c26dbc4ab4b891c978f8eac76e892af5765e6ac3 · Roger Ferrer / llvm-epi · GitLab

Nov 18, 2021
- [sanitizer] Fix DenseMap for compiler-rt · c26dbc4a
  Vitaly Buka authored Nov 17, 2021
  c26dbc4a
- [NFC][llvm] Inclusive language: reword and remove uses of sanity in llvm/lib/Target · 5b8bbbec
  Zarko Todorovski authored Nov 17, 2021
  5b8bbbec
- [X86][AMX] Don't emit tilerelease for old AMX instrisic. · c4dba471
  Luo, Yuanke authored Nov 17, 2021
  c4dba471
- Autogen a test for ease of update · 0623f52a
  Philip Reames authored Nov 17, 2021
  
  0623f52a
- [AMDGPU] Update GFX10 memory model to account for MALL · 6d28dffb
  Carl Ritson authored Nov 18, 2021
  6d28dffb
- [LegalizeTypes] Further limit expansion of CTTZ during type promotion. · d78fdf11
  Craig Topper authored Nov 17, 2021
  d78fdf11
Nov 17, 2021
- [SCEVAA] Avoid forming malformed pointer diff expressions · ad69402f
  Philip Reames authored Nov 17, 2021
  ad69402f
- Fix -Wparentheses warnings. NFC. · b861c360
  Michael Liao authored Nov 17, 2021
  
  b861c360
- [X86] splitVector - only extract lower half subvector from splats · 5f99f771
  Simon Pilgrim authored Nov 17, 2021
  5f99f771
- Fix MSVC signed/unsigned mismatch warning. NFC. · 3020608b
  Simon Pilgrim authored Nov 17, 2021
  
  3020608b
- [X86] LowerRotate - improve vXi8 rotate-by-scalar lowering with direct use of... · e76032c1
  Simon Pilgrim authored Nov 17, 2021
  e76032c1
- [InstCombine] Generalize complex OR patterns to AND · 6d3db280
  Stanislav Mekhanoshin authored Nov 09, 2021
  6d3db280
- [llvm-objcopy] Fix some comment typos · 1718fe46
  Nico Weber authored Nov 17, 2021
  
  1718fe46
- [llvm-objcopy][MachO] Add llvm-strip support for newer load commands · 68311f21
  Keith Smiley authored Nov 11, 2021
  68311f21
- [x86/asm] Let EmitMSInlineAsmStr() handle variants too · bf834b26
  Nico Weber authored Nov 15, 2021
  bf834b26
- [RISCV] Lower vector CTLZ_ZERO_UNDEF/CTTZ_ZERO_UNDEF by converting to FP and... · 0274be28
  Craig Topper authored Nov 17, 2021
  0274be28
- [x86/asm] Make variants work when converting at&t inline asm input to intel asm output · 103cc914
  Nico Weber authored Nov 15, 2021
  103cc914
- [llvm-objdump/mac] Add support for new load commands · 693b0202
  Keith Smiley authored Nov 11, 2021
  693b0202
- Fix the side effect of outlined function when the register is implicit use and... · 1e9fa0b1
  DianQK authored Nov 17, 2021
  1e9fa0b1
- [JITLink] Allow duplicate symbol names for locals · 52737735
  Ben Langmuir authored Nov 16, 2021
  52737735
- [gn build] Add missed comma · e1ef1406
  Arthur Eubanks authored Nov 17, 2021
  
  e1ef1406
- [NewPM] Add option to prevent rerunning function pipeline on functions in CGSCC adaptor · e3e25b51
  Arthur Eubanks authored Nov 16, 2021
  e3e25b51
- [SLP][NFC]Add a test for multiple alternate nodes with cost estimation, · 2e7f12d5
  Alexey Bataev authored Nov 17, 2021
  2e7f12d5
- [NFC][gn build] Inclusive language: replace master with main in sync_source_lists_from_cmake.py · 76313f8e
  Quinn Pham authored Nov 15, 2021
  76313f8e
- tsan: don't consider debug calls as calls · a7c57c4e
  Dmitry Vyukov authored Nov 17, 2021
  a7c57c4e
- [NFC][AMDGPU][GlobalISel] Fix some legalizer tests · f2d402e5
  Mirko Brkusanin authored Nov 17, 2021
  f2d402e5
- [AMDGPU][GlobalISel] Fold G_FNEG above when users cannot fold mods · db6bc2ab
  Mirko Brkusanin authored Nov 17, 2021
  db6bc2ab
- [Analysis] Ensure getTypeLegalizationCost returns a simple VT for TypeScalarizeScalableVector · 8d77555b
  David Sherwood authored Nov 12, 2021
  8d77555b
- [AMDGPU] Generate test checks for mad_64_32.ll · aeedbd39
  Jay Foad authored Nov 16, 2021
  aeedbd39
- [DAG] SimplifyDemandedVectorElts - zero_extend_vector_inreg(and(x,c)) -> and(x,c') · 5fedbd5b
  Simon Pilgrim authored Nov 17, 2021
  5fedbd5b
- [Analysis] Fix getNumberOfParts to return 0 when the answer is unknown · 670dd402
  David Sherwood authored Nov 11, 2021
  670dd402
- [DebugInfo][NFC] Force some tests to not use instruction-referencing · 1dc0e47c
  Jeremy Morse authored Nov 17, 2021
  1dc0e47c
- [Thumb2] Regenerate test impacted by e8b55cf7 . · 7b39ae51
  Florian Hahn authored Nov 17, 2021
  
  7b39ae51
- [SCEV] Apply loop guards when computing max BTC for arbitrary steps. · e8b55cf7
  Florian Hahn authored Nov 17, 2021
  e8b55cf7
- [IR] Change CreateStepVector to work with element types smaller than i8 · ca18fcc2
  David Sherwood authored Nov 12, 2021
  ca18fcc2
- [RISCV] Add extra -early-live-intervals test coverage · 4be705d6
  Jay Foad authored Oct 08, 2021
  4be705d6
- [CodeGen] Update LiveIntervals in TargetInstrInfo::convertToThreeAddress · 3264e959
  Jay Foad authored Nov 09, 2021
  3264e959
- [InstCombine] Use SpecificBinaryOp_match in two more places · c74f2e5b
  Stanislav Mekhanoshin authored Nov 16, 2021
  c74f2e5b
- [NFC][X86][Costmodel] Improve test coverage for i32->i64 vector *ext · 496ccb54
  Roman Lebedev authored Nov 17, 2021
  
  496ccb54
- [X86][Costmodel] `*ext v64i1 to v32i16` can appear after legalization, cost is... · 2037ec72
  Roman Lebedev authored Nov 17, 2021
  2037ec72