Commits · c494239bd85d909c7a0a7030a05a9221046db1ef · Roger Ferrer / llvm-epi · GitLab

Mar 06, 2017
- [TableGen] Ensure proper ordering of subtarget feature names · 03c5c215
  Krzysztof Parzyszek authored Mar 06, 2017
  03c5c215
- [Hexagon] Early-if-convert branches that may exit the loop · 8a4c601a
  Krzysztof Parzyszek authored Mar 06, 2017
  8a4c601a
- [Hexagon] Mark dead defs as <dead> in expand-condsets · e16ce156
  Krzysztof Parzyszek authored Mar 06, 2017
  e16ce156
- [Hexagon] Pick a dot-old instruction that matches the architecture · 143158b7
  Krzysztof Parzyszek authored Mar 06, 2017
  143158b7
- [DAGCombiner] simplify div/rem-by-0 · 7f7947bf
  Sanjay Patel authored Mar 06, 2017
  7f7947bf
- [x86] add tests to show missing div/rem simplifications; NFC · 9aad9347
  Sanjay Patel authored Mar 06, 2017
  9aad9347
- [PowerPC] Fix failure with STBRX when store is narrower than the bswap · 12e67d86
  Nemanja Ivanovic authored Mar 06, 2017
  12e67d86
- [XRay] Allow logging the first argument of a function call. · 7e8eea42
  Dean Michael Berris authored Mar 06, 2017
  7e8eea42
Mar 05, 2017
- [SelectionDAG] Fix vector splitting for *_EXTEND_VECTOR_INREG instructions · 584d6d9d
  Simon Pilgrim authored Mar 05, 2017
  584d6d9d
- [X86][SSE] Lower 128-bit vectors to SIGN/ZERO_EXTEND_VECTOR_IN_REG ops · 9f5c251d
  Simon Pilgrim authored Mar 05, 2017
  9f5c251d
Mar 04, 2017
- [x86] don't require a zext when forming ADC/SBB · b974be5e
  Sanjay Patel authored Mar 04, 2017
  b974be5e
- [DAGCombiner] allow transforming (select Cond, C +/- 1, C) to (add(ext Cond), C) · 066f3208
  Sanjay Patel authored Mar 04, 2017
  066f3208
- [X86][SSE] Enable post-legalize vXi64 shuffle combining on 32-bit targets · 40a0e66b
  Simon Pilgrim authored Mar 04, 2017
  40a0e66b
- [legalize-types] Remove stale entries from SoftenedFloats. · 6406f983
  Florian Hahn authored Mar 04, 2017
  6406f983
- X86ISelLowering: Only perform copy elision on legal types. · 21f340fd
  Matthias Braun authored Mar 04, 2017
  21f340fd
- [x86] check for commuted add pattern to find ADC/SBB · a84fd041
  Sanjay Patel authored Mar 04, 2017
  a84fd041
- [x86] add test to show failed recognition of commuted pattern; NFC · 71c1958f
  Sanjay Patel authored Mar 04, 2017
  71c1958f
- Revert r296865 "[ARM] fpscr read/write intrinsics not aware of each other" · 1c9d800f
  Hans Wennborg authored Mar 03, 2017
  1c9d800f
- GlobalISel: constrain G_INSERT to inserting just one value per instruction. · 3e6a7afd
  Tim Northover authored Mar 03, 2017
  3e6a7afd
Mar 03, 2017
- GlobalISel: add merge/unmerge nodes for legalization. · bf017293
  Tim Northover authored Mar 03, 2017
  bf017293
- [x86] regenerate checks; NFC · 000d61ac
  Sanjay Patel authored Mar 03, 2017
  000d61ac
- [x86] regenerate checks; NFC · 1716aa45
  Sanjay Patel authored Mar 03, 2017
  1716aa45
- [x86] regenerate checks; NFC · 9f5db7d4
  Sanjay Patel authored Mar 03, 2017
  9f5db7d4
- [x86] regenerate checks; NFC · 872e0b86
  Sanjay Patel authored Mar 03, 2017
  872e0b86
- [x86] regenerate checks; NFC · 6fa63167
  Sanjay Patel authored Mar 03, 2017
  6fa63167
- [ARM] fpscr read/write intrinsics not aware of each other · 7b60a9ed
  Ranjeet Singh authored Mar 03, 2017
  7b60a9ed
- [SDAG] Revert r296476 (and r296486, r296668, r296690). · ce52b807
  Chandler Carruth authored Mar 03, 2017
  ce52b807
- [X86] Generate VZEROUPPER for Skylake-avx512. · 4f977517
  Amjad Aboud authored Mar 03, 2017
  4f977517
- [GlobalISel][X86] Support float/double and vector types. · 321cf3c6
  Igor Breger authored Mar 03, 2017
  321cf3c6
- CodeGen: BlockPlacement: Precompute layout for chains of triangles. · 1fa60307
  Kyle Butt authored Mar 03, 2017
  1fa60307
Mar 02, 2017
- [DAGCombiner] Fix DebugLoc propagation when folding !(x cc y) -> (x !cc y) · 96c64156
  Taewook Oh authored Mar 02, 2017
  96c64156
- [Hexagon] Pick the right branch opcode depending on branch probabilities · e720feb1
  Krzysztof Parzyszek authored Mar 02, 2017
  e720feb1
- Revert "AMDGPU: Re-do update for branch-relaxation test" · 02d86b80
  Tobias Grosser authored Mar 02, 2017
  02d86b80
- CodeGen: MachineBlockPlacement: Remove the unused outlining heuristic. · 1393761e
  Kyle Butt authored Mar 02, 2017
  1393761e
- [ARM] Fix insert point for store rescheduling. · bb821276
  Eli Friedman authored Mar 02, 2017
  bb821276
- [PPC] Fix code generation for bswap(int32) followed by store16 · ed28e742
  Guozhi Wei authored Mar 02, 2017
  ed28e742
- [AArch64] Extend redundant copy elimination pass to handle non-zero stores. · ea25eca0
  Chad Rosier authored Mar 02, 2017
  ea25eca0
- [MSP430] Add SRet support to MSP430 target · eafb8055
  Vadzim Dambrouski authored Mar 02, 2017
  eafb8055
- [X86][MMX] Fixed i32 extraction on 32-bit targets · b3067dc3
  Simon Pilgrim authored Mar 02, 2017
  b3067dc3
- [Hexagon] Skip blocks that define vector predicate registers in early-if · 056c945a
  Krzysztof Parzyszek authored Mar 02, 2017
  056c945a