Commits · cfb3ee21857da7c3d96f89afc3fecb0ec833dde9 · Roger Ferrer / llvm-epi · GitLab

Apr 13, 2022
- [DAG] Add non-uniform vector support to (shl (srl x, c1), c2) -> (and (shift x, c3)) · cfb3ee21
  Simon Pilgrim authored Apr 13, 2022
  cfb3ee21
- [RISCV][NFC] Reorganize check prefixes in some tests to reduce redundant lines · 9d2350fd
  Ping Deng authored Apr 13, 2022
  9d2350fd
- [AArch64] Add missing HasNEON predicate in scalar FABD patterns · ee44896c
  Alex Richardson authored Apr 12, 2022
  ee44896c
- [AArch64] Baseline test for D123491 · 32a353a5
  Alex Richardson authored Apr 11, 2022
  
  32a353a5
- [AArch64][SVE] Fix lowering of "fcmp ueq/one" when using SVE · 44271e7c
  David Sherwood authored Mar 17, 2022
  44271e7c
- Support the min of module flags when linking, use for AArch64 BTI/PAC-RET · b0343a38
  Daniel Kiss authored Apr 13, 2022
  b0343a38
- AMDGPU: Update reqd-work-group-size optimization for umin intrinsic · c986d476
  Matt Arsenault authored Apr 07, 2022
  c986d476
- RegAllocGreedy: Fix illegal eviction assert for urgent evictions · d4b1be20
  Matt Arsenault authored Mar 29, 2022
  d4b1be20
- [AMDGPU] Split unaligned 4 DWORD DS operations · f6462a26
  Stanislav Mekhanoshin authored Apr 11, 2022
  f6462a26
- RegAllocGreedy: Roll back successful recolorings on failure · eefed1db
  Matt Arsenault authored Mar 17, 2022
  eefed1db
Apr 12, 2022
- [NVPTX][FIX] Allow __nvvm_reflect in the presence of opaque pointers · 0f070bee
  Johannes Doerfert authored Apr 11, 2022
  0f070bee
- AMDGPU: Don't use unreachable on stores to unhandled address space · 788f94f7
  Matt Arsenault authored Feb 21, 2022
  788f94f7
- AArch64/GlobalISel: Remove pointless s1 legalize rules · 60091222
  Matt Arsenault authored Apr 11, 2022
  60091222
- GlobalISel: Fix lowerSelect handling of boolean high bits · 3f2cc7cc
  Matt Arsenault authored Apr 11, 2022
  3f2cc7cc
- Mips/GlobalISel: Add test for atomic load · 120c5115
  Matt Arsenault authored Apr 10, 2022
  
  120c5115
- AMDGPU: Emit metadata for the hidden_multigrid_sync_arg conditionally · 8edaf259
  Changpeng Fang authored Apr 12, 2022
  8edaf259
- [AMDGPU] Update ds-alignment.ll test checks. NFC. · 65b8a432
  Stanislav Mekhanoshin authored Apr 12, 2022
  
  65b8a432
- [AArch64][LOH] Don't ignore regmasks in bundles by iterating over instrs. · cfa4fe7c
  Ahmed Bougacha authored Apr 12, 2022
  cfa4fe7c
- [AArch64] Cleanup call-rv-marker.ll test. NFC. · f3e76dca
  Ahmed Bougacha authored Apr 12, 2022
  f3e76dca
- [AArch64] Async unwind - function epilogues · d0ea42a7
  Momchil Velikov authored Apr 12, 2022
  d0ea42a7
- [AMDGPU] Split unaligned 3 DWORD DS operations · 3870b360
  Stanislav Mekhanoshin authored Apr 11, 2022
  3870b360
- [AMDGPU] Refactor LDS alignment checks. · b8e09f15
  Stanislav Mekhanoshin authored Apr 06, 2022
  b8e09f15
- [DAG] Add non-uniform vector support to (shl (sr[la] exact X, C1), C2) folds · bc32a1dd
  Simon Pilgrim authored Apr 12, 2022
  
  bc32a1dd
- [X86] Fix extact -> exact typo in test names · bb1a1f42
  Simon Pilgrim authored Apr 12, 2022
  
  bb1a1f42
- [AMDGPU] Graceful abort for waterfalls in SIOptimizeVGPRLiveRange · 2bca7d85
  Carl Ritson authored Apr 12, 2022
  2bca7d85
- [AMDGPU] Pre-commit test for D123569. NFC. · 4c59fc53
  Carl Ritson authored Apr 12, 2022
  
  4c59fc53
- GlobalISel: Verify atomic load/store ordering restriction · 5a5034d5
  Matt Arsenault authored Apr 10, 2022
  5a5034d5
- AArch64/GlobalISel: Regenerate mir test checks · 7e8ff962
  Matt Arsenault authored Apr 09, 2022
  7e8ff962
- GlobalISel: Add memSizeNotByteSizePow2 legality helper · d1f97a34
  Matt Arsenault authored Apr 10, 2022
  d1f97a34
- GlobalISel: Implement computeKnownBits for overflow bool results · 1416744f
  Matt Arsenault authored Apr 11, 2022
  
  1416744f
- AMDGPU/GlobalISel: Add some additional IR tests for zextload · eee82dc6
  Matt Arsenault authored Apr 10, 2022
  
  eee82dc6
- AMDGPU/GlobalISel: Add more tests for inreg extend + load combine · 4c037bdb
  Matt Arsenault authored Apr 10, 2022
  
  4c037bdb
- Mips/GlobalISel: Remove test IR sections and regenerate checks · 3f3ff0e4
  Matt Arsenault authored Apr 10, 2022
  
  3f3ff0e4
- AArch64/GlobalISel: Remove IR section from a test · 492d0eab
  Matt Arsenault authored Apr 10, 2022
  
  492d0eab
- Reapply "AMDGPU: Remove AMDGPUFixFunctionBitcasts pass" · 203a1e36
  Matt Arsenault authored Dec 17, 2021
  203a1e36
- AMDGPU: Align the implicit kernel argument segment to 8 bytes for v5 · 7f9868f9
  Changpeng Fang authored Apr 11, 2022
  7f9868f9
Apr 11, 2022
- [RISCV][SelectionDAG] Add a hook to sign extend i32 ConstantInt operands of phis on RV64. · 2ce25628
  Craig Topper authored Apr 11, 2022
  2ce25628
- AArch64 adding more tests to show the simple scenarios for or/and combine · d06fb904
  Biplob Mishra authored Apr 11, 2022
  
  d06fb904
- AMDGPU/SDAG: Custom SETCC (i.e. ballot) is always uniform · 4df4922d
  Nicolai Hähnle authored Apr 08, 2022
  4df4922d
- [RISCV] Remove riscv-v-fixed-length-vector-elen-max command line option. · 76192182
  Craig Topper authored Apr 11, 2022
  76192182