Commits · d092dd56aed8af64425446544ca7c9a0616d86ce · Roger Ferrer / llvm-epi · GitLab

May 11, 2021
- [AArch64][GlobaISel] Mark target generic instructions as HasNoSideEffects. · 69069509
  Amara Emerson authored May 10, 2021
  69069509
- [AArch64][GlobalISel] Support truncstorei8/i16 w/ combine to form truncating G_STOREs. · ae2b36e8
  Amara Emerson authored Jan 24, 2021
  ae2b36e8
- [AArch64][GlobalISel] Add post-legalizer lowering for NEON vector fcmps · 79be9c59
  Jessica Paquette authored May 03, 2021
  79be9c59
- [AArch64][GlobalISel] Enable memcpy family combines on minsize functions · 6d8b070d
  Jessica Paquette authored May 10, 2021
  6d8b070d
May 10, 2021
- [TargetLowering] Only inspect attributes in the arguments for ArgListEntry · 16748bd2
  Arthur Eubanks authored May 03, 2021
  16748bd2
- [GlobalISel][IRTranslator] Fix bit-test lowering dropping phi edges. · dc754999
  Amara Emerson authored May 10, 2021
  dc754999
- [AArch64][SVE] Improve SVE codegen for fixed length BITCAST · 635164b9
  Bradley Smith authored May 06, 2021
  635164b9
- [AArch64][SVE] Better utilisation of unpredicated forms of remaining intrinsics · 65c89cd1
  Bradley Smith authored Apr 30, 2021
  65c89cd1
- [AArch64][SVE] Better utilisation of unpredicated forms of arithmetic intrinsics · f8f953c2
  Bradley Smith authored Apr 30, 2021
  f8f953c2
- [AArch64][SVE] Fix isel failure for FP-extending loads · 407a3388
  Sander de Smalen authored May 10, 2021
  407a3388
May 08, 2021
- [AArch64][GlobalISel] Create a new minimal combiner pass just for -O0. · 5b158093
  Amara Emerson authored May 06, 2021
  5b158093
- [GlobalISel] Don't form zero/sign extending loads for atomics. · 808bc11d
  Amara Emerson authored May 05, 2021
  808bc11d
May 07, 2021
- [AArch64][GlobalISel] Legalize narrow type G_CTPOPs · 13128520
  Jessica Paquette authored Apr 20, 2021
  13128520
- [AArch64][ELF] Prefer to lower MC_GlobalAddress operands to .Lfoo$local · 6a2850f3
  Fangrui Song authored May 07, 2021
  6a2850f3
- [DAG] Add a generic expansion for SHIFT_PARTS opcodes using funnel shifts · 280aa341
  Simon Pilgrim authored May 07, 2021
  280aa341
May 05, 2021
- GlobalISel: Use DAG call lowering infrastructure in a more compatible way · fa0b93b5
  Matt Arsenault authored Apr 13, 2021
  fa0b93b5
- [AArch64] Fix for the pre-indexed paired load/store optimization. · 3f4bad5e
  Stelios Ioannou authored May 05, 2021
  3f4bad5e
- [AArch64] Fix scalar imm variants of SIMD shift left instructions · 1ee50b47
  Andrew Savonichev authored Apr 29, 2021
  1ee50b47
May 04, 2021
- [AArch64][SVE] Fold insert(zero, extract(X, 0), 0) -> X, when X is known to zero lanes 1-N · 9f37980d
  Bradley Smith authored Apr 27, 2021
  9f37980d
- Recommit "[VP,Integer,#2] ExpandVectorPredication pass" · 1db4dbba
  Simon Moll authored Apr 30, 2021
  1db4dbba
- [AArch64][SVE] More unpredicated ld1/st1 patterns for reg+reg addressing modes · 8a40bf6d
  Eli Friedman authored Apr 14, 2021
  8a40bf6d
May 03, 2021
- [AArch64] Fold CSEL x, x, cc -> x · 966435da
  David Green authored May 03, 2021
  966435da
- [AArch64] Sets the preferred function alignment for Cortex-A53/A55. · 36a44dfd
  Stelios Ioannou authored Apr 30, 2021
  36a44dfd
May 01, 2021
- [AArch64] Prevent spilling between ldxr/stxr pairs · 4751cadc
  LemonBoy authored May 01, 2021
  4751cadc
- [NFC][ARM] Regenerate arm64-atomic.ll test · 5a42538b
  LemonBoy authored May 01, 2021
  5a42538b
- Revert "[NFC][ARM] Regenerate arm64-atomic.ll test" · 83c540dc
  LemonBoy authored May 01, 2021
  83c540dc
- [NFC][ARM] Regenerate arm64-atomic.ll test · d9856b12
  LemonBoy authored May 01, 2021
  d9856b12
- Revert "[VP,Integer,#2] ExpandVectorPredication pass" · 02c5ba86
  Adrian Prantl authored Apr 30, 2021
  02c5ba86
- [EarlyIfConversion] Avoid producing selects with identical operands · 421569b2
  Jon Roelofs authored Apr 29, 2021
  421569b2
Apr 30, 2021
- Revert "[EarlyIfConversion] Avoid producing selects with identical operands" · 8be3af36
  Jon Roelofs authored Apr 30, 2021
  8be3af36
- [EarlyIfConversion] Avoid producing selects with identical operands · 3d27b5d2
  Jon Roelofs authored Apr 29, 2021
  3d27b5d2
- [AArch64] Fix lowering for fshl/fshr with SVE types. · 6e6ae6c7
  Eli Friedman authored Apr 29, 2021
  6e6ae6c7
- [AArch64] Adds a pre-indexed paired Load/Store optimization for LDR-STR. · 936c777e
  Stelios Ioannou authored Apr 30, 2021
  936c777e
- [VP,Integer,#2] ExpandVectorPredication pass · 43bc584d
  Simon Moll authored Apr 30, 2021
  43bc584d
- [AArch64][SVE] Lower index_vector to step_vector · b310dd15
  Jun Ma authored Apr 20, 2021
  b310dd15
- [AArch64][GlobalISel] Fix width value for G_SBFX/G_UBFX · d7d85f72
  Brendon Cahoon authored Apr 29, 2021
  d7d85f72
Apr 29, 2021
- [AArch64][GlobalISel] Simplify out of range rotate amount. · 96ec6d91
  Amara Emerson authored Apr 26, 2021
  96ec6d91
- [AArch64][SVE] Use SIMD variant of INSR when scalar is the result of a vector extract · 354604a2
  Bradley Smith authored Apr 23, 2021
  354604a2
- [AArch64][SVE] Move convert.{from,to}.svbool optimization into InstCombine · c8f20ed4
  Bradley Smith authored Apr 26, 2021
  c8f20ed4
Apr 28, 2021
- [AArch64][GlobalISel] Don't match thread-local globals in matchFoldGlobalOffset · 4d41810c
  Jessica Paquette authored Apr 28, 2021
  4d41810c