Commits · d26344731128ccdd8eeb27a12b2c3bd75e5e3a63 · Roger Ferrer / llvm-epi · GitLab

Jul 05, 2022
- [AMDGPU][GlobalISel] Support register offsets for SMRDs. · 8cd79bc1
  Ivan Kosarev authored Jul 05, 2022
  8cd79bc1
- [VE] Restructure eliminateFrameIndex · da5a6b2b
  Kazushi (Jam) Marukawa authored Jul 05, 2022
  da5a6b2b
- Revert "[VE] Restructure eliminateFrameIndex" · 9ad38e52
  Kazushi (Jam) Marukawa authored Jul 05, 2022
  9ad38e52
- [VE] Restructure eliminateFrameIndex · 98e52e8b
  Kazushi (Jam) Marukawa authored Jul 02, 2022
  98e52e8b
- [ARM] Add Support for Cortex-M85 · 1666f099
  Archibald Elliott authored Jul 05, 2022
  1666f099
- [AArch64][SME] Add SME addha/va intrinsics · 77b13a57
  David Sherwood authored Jun 15, 2022
  77b13a57
- [LoongArch] Add initial support for function calls · 3610d5f5
  wanglei authored Jul 05, 2022
  3610d5f5
- [LoongArch] Add codegen support for conditional branches · b940fe6f
  wanglei authored Jul 05, 2022
  b940fe6f
- [LoongArch] Add codegen support for load/store operations · 5b4851ed
  wanglei authored Jul 05, 2022
  5b4851ed
Jul 04, 2022
- [X86] Regenerate fold-tied-op.ll test checks · 623250b5
  Simon Pilgrim authored Jul 04, 2022
  
  623250b5
- [AArch64] Add support for insert/extract for nxv1i1 types. · 5785717e
  Sander de Smalen authored Jul 04, 2022
  5785717e
- [X86] Disable combineVectorSizedSetCCEquality for soft float. · 2bfca356
  Craig Topper authored Jul 04, 2022
  2bfca356
- [RISCV] Add ADDI instr for computing FrameIndex address · c06d0b4d
  luxufan authored Jun 19, 2022
  c06d0b4d
- [AArch64] Add additional tests for D120481. · f0089fae
  Florian Hahn authored Jul 04, 2022
  
  f0089fae
- [IR] Remove support for insertvalue constant expression · 7283f48a
  Nikita Popov authored Jun 28, 2022
  7283f48a
- [RISCV] Add more SHXADD patterns. · d36e09cf
  Craig Topper authored Jul 03, 2022
  d36e09cf
- [AIX] Handling the label alignment of a global · d2a35e4d
  esmeyi authored Jul 03, 2022
  d2a35e4d
Jul 03, 2022
- [AArch64] Regenerate more tests. NFC · d100a30a
  David Green authored Jul 03, 2022
  d100a30a
- [RISCV] Add a scavenge spill slot when use ADDI to compute scalable stack offset · 0f45eaf0
  luxufan authored Jun 18, 2022
  0f45eaf0
- [RISCV] Add more SHXADD isel patterns. · 7e4ab9d5
  Craig Topper authored Jul 02, 2022
  7e4ab9d5
Jul 02, 2022
- [RISCV] isel (shl (and X, C2), C) -> (slli (srliw X, C3), C3+C). · b2e9684f
  Craig Topper authored Jul 02, 2022
  b2e9684f
- [RISCV] isel (add (and X, 0xFFFFFFFE), Y) as (SH1ADD (SRLIW X, 1), Y). · 9ac548e1
  Craig Topper authored Jul 01, 2022
  9ac548e1
- [RISCV] Restore "Enable shrink wrap by default" · 5744b9cb
  Yeting Kuo authored Jul 01, 2022
  5744b9cb
Jul 01, 2022
- [DirectX] add thread/group id DXIL operations. · 43dc3190
  Xiang Li authored Jun 16, 2022
  43dc3190
- [AArch64] Make nxv1i1 types a legal type for SVE. · 690db164
  Sander de Smalen authored Jul 01, 2022
  690db164
- [SVE][AArch64] Refine hasSVEArgsOrReturn · 5166345f
  Matt Devereau authored Jun 07, 2022
  5166345f
- [AMDGPU][GlobalISel] Always use VGPR bank for G_FCMP · 2208342c
  Mirko Brkusanin authored Jul 01, 2022
  2208342c
- Revert rG057db2002bb3: [X86] combineAndnp - constant fold ANDNP(C,X) -> AND(~C,X) · 26708fa1
  Simon Pilgrim authored Jul 01, 2022
  26708fa1
- [AMDGPU] Update WMMA intrinsics with explicit f16 types · b6ef36a1
  Piotr Sobczak authored Jul 01, 2022
  b6ef36a1
- [ISel] Match all bits when merge undefs for DAG combine · 72a23cef
  Xiang1 Zhang authored Jul 01, 2022
  72a23cef
- Revert "[ISel] Match all bits when merge undef(s) for DAG combine" · 64f44a90
  Xiang1 Zhang authored Jul 01, 2022
  64f44a90
- [ISel] Match all bits when merge undef(s) for DAG combine · 5fe5aa28
  Xiang1 Zhang authored Jun 30, 2022
  
  5fe5aa28
- [X86] Pre-commit tests for D128769. NFC · eec5d040
  Craig Topper authored Jun 28, 2022
  
  eec5d040
- [SVE] Use CPY to zero active lanes of a floating point vector. · 43f8a6b7
  Paul Walker authored Jun 24, 2022
  43f8a6b7
- [SVE] Extend "and(ipg,cmp(x,y))" patterns to cover the case when y is an immediate. · 2be4a7a2
  Paul Walker authored Jun 22, 2022
  2be4a7a2
- [VE] Support load/store vm regsiters · adbb46ea
  Kazushi (Jam) Marukawa authored Jun 25, 2022
  adbb46ea
Jun 30, 2022
- [RISCV] Make custom isel for (add X, imm) used by load/stores more selective. · 354e0455
  Craig Topper authored Jun 30, 2022
  354e0455
- [AMDGPU] Make v16i16/v16f16 legal · bd675af2
  Piotr Sobczak authored Jun 30, 2022
  bd675af2
- [AMDGPU] GFX11: automatically release VGPRs at the end of the shader · 0f94d2b3
  Jay Foad authored Jun 30, 2022
  0f94d2b3
- [AMDGPU] add alternate tests for max-offset codegen; NFC · e44dcfb0
  Sanjay Patel authored Jun 30, 2022
  e44dcfb0