Commits · d42f76fd368ac885289836c0bce1d7ca6ad7348a · Roger Ferrer / llvm-epi · GitLab

Sep 09, 2021
- [AArch64][SVE] NFC: Remove unused template args · d42f76fd
  Cullen Rhodes authored Sep 09, 2021
  d42f76fd
- [AArch64][SVE] NFC: Use stepvector directly in index multiclasses · 5b848a35
  Cullen Rhodes authored Sep 09, 2021
  5b848a35
- [RISCV] Add SiFive cores E and S series · 4bc8dbe0
  Alexander Pivovarov authored Sep 03, 2021
  4bc8dbe0
- [RISCV] Fix Machine Outliner jump table handling. · 261cbe98
  Yvan Roux authored Sep 09, 2021
  261cbe98
- [MachineOutliner][AArch64] Ensure LR is live-in when inserting reg-save calls · 22a64d4a
  Jessica Paquette authored Sep 08, 2021
  22a64d4a
Sep 08, 2021
- [RISCV] Disable use of i128 shift libcalls on RV32. · a574f0e0
  Craig Topper authored Sep 08, 2021
  a574f0e0
- [ObjC][ARC] Use the addresses of the ARC runtime functions instead of · dea6f71a
  Akira Hatanaka authored Sep 08, 2021
  dea6f71a
- [asan] Fixed the jump to use the 4 byte offset version. · 3f875134
  Kirill Stoimenov authored Sep 08, 2021
  3f875134
- [WebAssembly] Change WebAssemblyMCLowerPrePass to ModulePass · a99fb86c
  Wouter van Oortmerssen authored Sep 02, 2021
  a99fb86c
- [RISCV] Remove unused tablegen template parameters. NFC · aca14c8c
  Craig Topper authored Sep 08, 2021
  aca14c8c
- [RISCV] Use V0 instead of VMV0: for mask vectors in isel patterns. · b04c09c0
  Craig Topper authored Sep 08, 2021
  b04c09c0
- [X86] X86DAGToDAGISel::matchBitExtract(): support 'num high bits to clear' pattern · 0852f870
  Roman Lebedev authored Sep 08, 2021
  0852f870
- [RISCV] Add an GPR def to the Zvlseg SPILL/RELOAD pseudos · 1f161919
  Craig Topper authored Sep 08, 2021
  1f161919
- [AArch64][SME] Fix imm bug in mov vector to tile aliases · 89786c2b
  Cullen Rhodes authored Sep 07, 2021
  89786c2b
- [AArch64] Implement extract_subvector for predicates. · 981f7d56
  Sander de Smalen authored Sep 07, 2021
  981f7d56
- [AVR] Add support for the tinyAVR 0-series and tinyAVR 1-series · b0d4d969
  Justin Latimer authored Sep 08, 2021
  b0d4d969
- [AArch64] Improve target hook function to decide folding (mul (add x, c1), c2) · f0460fa4
  Ben Shi authored Sep 04, 2021
  f0460fa4
- [X86][MS] Fix the aligement mismatch of vector variable arguments on Win32 · 9d7d34c7
  Wang, Pengfei authored Sep 08, 2021
  9d7d34c7
- [WebAssembly] Error out on indirect uses of setjmp · a1d52293
  Heejin Ahn authored Sep 03, 2021
  a1d52293
Sep 07, 2021
- [AArch64][Global ISel] Add sext/zext of vector extract improvements · 7023cefe
  Irina Dobrescu authored Sep 07, 2021
  7023cefe
- [X86] Don't clobber EBX in stackprobes · ae8507b0
  Elliot Saba authored Sep 07, 2021
  ae8507b0
- [X86ISelLowering] avoid emitting libcalls to __mulodi4() · d0eeb64b
  Nick Desaulniers authored Sep 07, 2021
  d0eeb64b
- [X86] X86InstrAVX512.td - remove unused template parameters. NFC. · 9eda4721
  Simon Pilgrim authored Sep 07, 2021
  9eda4721
- [Analysis, Target, Transforms] Construct SmallVector with iterator ranges (NFC) · 5648f717
  Kazu Hirata authored Sep 07, 2021
  
  5648f717
- [RISCV] Fix "set but not used" warnings · 5c6338de
  Kazu Hirata authored Sep 07, 2021
  
  5c6338de
- [PowerPC] Fixed the crash due to early if conversion with fixed CR fields · 4a226529
  Victor Huang authored Aug 30, 2021
  4a226529
- [X86] Add missing domain to avx512_ord_cmp_sae comis sae patterns · f8d2cd14
  Simon Pilgrim authored Sep 07, 2021
  f8d2cd14
- [PowerPC] Guard XSRSP in P8 for FastISel · 042a6564
  Jinsong Ji authored Sep 07, 2021
  042a6564
- [AArch64][SVE] Improve extract_subvector for predicates. · bd576e5a
  Sander de Smalen authored Sep 07, 2021
  bd576e5a
- [MC] Use local MCSubtargetInfo in writeNops · e63455d5
  Peter Smith authored Aug 09, 2021
  e63455d5
- [MC] Add MCSubtargetInfo to MCAlignFragment · 5e71839f
  Peter Smith authored Aug 06, 2021
  5e71839f
- [amdgpu] Enable selection of `s_cselect_b64`. · 640beb38
  Michael Liao authored Aug 30, 2021
  640beb38
- [AMDGPU][GlobalISel] Legalize G_MUL for non-standard types · 6c4b634d
  Mirko Brkusanin authored Sep 07, 2021
  6c4b634d
- [AMDGPU][GlobalISel] Legalization of G_ROTL and G_ROTR · 5263bf58
  Mirko Brkusanin authored Sep 07, 2021
  5263bf58
- [X86] X86InstrSSE.td - remove unused template parameters. NFC. · 0d48ee27
  Simon Pilgrim authored Sep 07, 2021
  0d48ee27
- [X86] X86InstrVecCompiler.td - remove unused template parameters. NFC. · b50a60c2
  Simon Pilgrim authored Sep 07, 2021
  b50a60c2
- [X86] X86InstrFMA.td - remove unused template parameters. NFC. · fb387950
  Simon Pilgrim authored Sep 07, 2021
  fb387950
- [AArch64][SVE] Implement all-inactive predicate with PFALSE. · 448d47f7
  Sander de Smalen authored Sep 07, 2021
  448d47f7
- [AMDGPU][GlobalISel] Legalize memcpy family of intrinsics · 36527cbe
  Mirko Brkusanin authored Sep 07, 2021
  36527cbe
- [RISCV][VP] Custom lower VP_STORE and VP_LOAD · a823bdf3
  Fraser Cormack authored Aug 31, 2021
  a823bdf3