Commits · d4cb5d9f2ba636b0049fc5791d378e224e3a3ae7 · Roger Ferrer / llvm-epi · GitLab

Jan 17, 2024
- [X86] Add "Ws" constraint and "p" modifier for symbolic address/label reference (#77886) · d4cb5d9f
  Fangrui Song authored Jan 16, 2024
  d4cb5d9f
- [RISCV][GISel] Don't create generic virtual registers in selectSHXADDOp/selectSHXADD_UWOp. (#78396) · 00d6232d
  Craig Topper authored Jan 16, 2024
  00d6232d
- [X86] Use vXi1 for `k` constraint in inline asm (#77733) · 8d6e82d5
  Phoebe Wang authored Jan 17, 2024
  8d6e82d5
- [LoongArch] Add LoongArch V1.1 instructions definitions and MC tests (#78238) · 84bdee28
  Ami-zhang authored Jan 17, 2024
  84bdee28
- [X86][BF16] Improve float -> bfloat lowering under AVX512BF16 and AVXNECONVERT (#78042) · 9745c13c
  Phoebe Wang authored Jan 17, 2024
  
  9745c13c
- Revert "[AMDGPU] Sign extend simm16 in setreg intrinsic" (#78372) · f3190c78
  Florian Mayer authored Jan 16, 2024
  f3190c78
- [llvm] Indirect symbol replacement with GOTPCREL for aarch64 and risc… (#78003) · e9e3e9d2
  PiJoules authored Jan 16, 2024
  e9e3e9d2
Jan 16, 2024
- [AMDGPU] Fix predicates for V_DOT instructions. (#78198) · 03abf7fe
  Ivan Kosarev authored Jan 16, 2024
  03abf7fe
- [NVPTX] Fix generating permute bytes from register pair when the initial... · aa23e493
  mmoadeli authored Jan 16, 2024
  aa23e493
- [NFC] sentinal -> sentinel · 7850c94b
  David Green authored Jan 16, 2024
  
  7850c94b
- [AMDGPU] Sign extend simm16 in setreg intrinsic (#77997) · 371fdbaa
  Stanislav Mekhanoshin authored Jan 16, 2024
  371fdbaa
- [RISCV] Add scheduler model for sifive-p450. (#77989) · 847c7872
  Craig Topper authored Jan 16, 2024
  847c7872
- [AArch64][SME2] Add ZT0 attributes to SMEAttrs (#77607) · a4ec04ea
  Kerry McLaughlin authored Jan 16, 2024
  a4ec04ea
- [X86][NFC] Simplify the patterns of BMI shift/rotate instructions in X86InstrCompiler.td · 6c1b5ec2
  Shengchen Kan authored Jan 16, 2024
  6c1b5ec2
- [SPARC] Prefer RDPC over CALL to implement GETPCX for 64-bit target · 118d4234
  Koakuma authored Jan 16, 2024
  118d4234
- [X86][NFC] Simplify the patterns of BMI shift/rotate instructions in X86InstrShiftRotate.td · dfaf09b5
  Shengchen Kan authored Jan 16, 2024
  dfaf09b5
- [RISCV] CodeGen of RVE and ilp32e/lp64e ABIs (#76777) · 3ac9fe69
  Pengcheng Wang authored Jan 16, 2024
  3ac9fe69
- [X86][NFC] Simplify the definitions of BMI shift/rotate instructions · 86bc18ad
  Shengchen Kan authored Jan 16, 2024
  
  86bc18ad
- [ARM] Add missing earlyclobber to sqrshr and uqrshl instructions. (#77782) · 60c77576
  Alfie Richards authored Jan 16, 2024
  60c77576
- [ARM] Fix phi operand order issue in MVEGatherScatterLowering (#78208) · 1074b94f
  David Green authored Jan 16, 2024
  1074b94f
- [AMDGPU] Remove VT helpers isFloatType, isPackedType, simplify isIntType (#77987) · 8e9e4f88
  Stanislav Mekhanoshin authored Jan 16, 2024
  
  8e9e4f88
- [AArch64] Fix a typo in predicate expression (NFC) (#78162) · c4c53aee
  Momchil Velikov authored Jan 16, 2024
  c4c53aee
- [X86][NFC] Simplify the definitions of double precision shift instructions · 2c4a53ad
  Shengchen Kan authored Jan 16, 2024
  
  2c4a53ad
- AMDGPU/GlobalISel: Handle inreg arguments as SGPRs (#78123) · 480cc413
  Matt Arsenault authored Jan 16, 2024
  480cc413
- [MachineScheduler] Add option to control reordering for store/load clustering (#75338) · 84f7fb62
  Alex Bradbury authored Jan 16, 2024
  84f7fb62
- [RISCV] Implement RISCVInsrInfo::getConstValDefinedInReg (#77610) · 57d517c2
  Alex Bradbury authored Jan 16, 2024
  57d517c2
- [RISCV] Remove vmv.s.x and vmv.x.s lmul pseudo variants (#71501) · 286a366d
  Luke Lau authored Jan 16, 2024
  286a366d
- [LoongArch] Add relaxDwarfLineAddr and relaxDwarfCFA to handle the mutable... · ed7f4edc
  Jinyang He authored Jan 16, 2024
  ed7f4edc
- [X86] Fix error: unused variable 'isMemOp' after #78019, NFCI · 199117ae
  Shengchen Kan authored Jan 16, 2024
  199117ae
- [AMDGPU][MC] Remove incorrect `_e32` suffix from `v_dot2c_f32_f16` and `v_dot4c_i32_i8` (#77993) · d63c2e52
  Shilei Tian authored Jan 15, 2024
  d63c2e52
- [X86] Fix -Wunused-variable in X86InstrInfo.cpp (NFC) · d338d152
  Jie Fu authored Jan 16, 2024
  d338d152
- [SPIR-V] Do not emit spv_ptrcast if GEP result is of expected type (#78122) · 59e5cb7b
  Michal Paszkowski authored Jan 15, 2024
  59e5cb7b
- [X86][NFC] Simplify the definitions of rotate instructions · 3d682174
  Shengchen Kan authored Jan 16, 2024
  
  3d682174
- [X86] Add MI-layer routine for getting the index of the first address operand, NFC (#78019) · 855e8630
  Nicholas Mosier authored Jan 15, 2024
  855e8630
Jan 15, 2024
- [llvm][MC][ARM] Don't autoresolve fixups (#76574) · c0944f52
  Eleanor Bonnici authored Jan 15, 2024
  c0944f52
- [SystemZ] Don't use FP Load and Test as comparisons to same reg (#78074) · 1d189309
  Jonas Paulsson authored Jan 15, 2024
  1d189309
- [AArch64][GlobalISel] Combine vecreduce(ext) to {U/S}ADDLV (#75832) · 927b8a0f
  chuongg3 authored Jan 15, 2024
  
  927b8a0f
- [AMDGPU] Do not generate s_set_inst_prefetch_distance for GFX12 (#78190) · ba131b70
  Jay Foad authored Jan 15, 2024
  ba131b70
- [AMDGPU] Disable hasVALUPartialForwardingHazard for GFX12 (#78188) · ed60cb8f
  Jay Foad authored Jan 15, 2024
  
  ed60cb8f
- [AMDGPU] Disable hasVALUMaskWriteHazard for GFX12 (#78187) · 85705bbf
  Jay Foad authored Jan 15, 2024
  
  85705bbf