Commits · d6de1e1a71406c75a4ea4d5a2fe84289f07ea3a1 · Roger Ferrer / llvm-epi · GitLab

Apr 17, 2021
- Normalize interaction with boolean attributes · d6de1e1a
  Serge Guelton authored Mar 24, 2021
  d6de1e1a
- [PowerPC] Minor improvement for insert_vector_elt codegen · ff769dd1
  Nemanja Ivanovic authored Apr 16, 2021
  ff769dd1
Apr 16, 2021
- [AMDGPU] Remove redundant field from DPP8 def · a0ed70ab
  Joe Nash authored Apr 16, 2021
  a0ed70ab
- [AMDGPU] NFC, Comment in disassembler for dpp8 · 919236e6
  Joe Nash authored Apr 16, 2021
  919236e6
- [WebAssembly] Remove saturating fp-to-int target intrinsics · 5c729750
  Thomas Lively authored Apr 16, 2021
  5c729750
- [AMDGPU] Remove dead dcode (NFC). · 97618522
  Christudasan Devadasan authored Apr 16, 2021
  
  97618522
- [AMDGPU] Refactor VOP3P Profile and AsmParser, NFC · 7cc4a02f
  Joe Nash authored Apr 15, 2021
  7cc4a02f
- [ARM] Prevent phi-node-elimination from generating copy above t2WhileLoopStartLR · 093f1828
  Malhar Jajoo authored Apr 16, 2021
  093f1828
- [X86][CostModel] Fix cost model for non-power-of-two vector load/stores · b06c55a6
  Roman Lebedev authored Apr 16, 2021
  b06c55a6
- [ARM] Combine sub 0, csinc X, Y, CC -> csinv -X, Y, CC · 00a60454
  David Green authored Apr 16, 2021
  00a60454
- [Aarch64] handle "o" inline asm memory constraints · bb7016f8
  Nick Desaulniers authored Apr 15, 2021
  bb7016f8
- [RISCV] Don't emit save-restore call if function is a interrupt handler · 2893570e
  Jim Lin authored Apr 16, 2021
  2893570e
- [AMDGPU] Refactor ds_read/ds_write related select code for better readability. · 099dcb68
  hsmahesha authored Apr 16, 2021
  099dcb68
Apr 15, 2021
- [clang][AArch64] Correctly align HFA arguments when passed on the stack · f9d932e6
  Momchil Velikov authored Apr 15, 2021
  f9d932e6
- [AMDGPU] Factor out predicate FmaakFmamkF32Insts · 13015ebd
  Stanislav Mekhanoshin authored Apr 13, 2021
  13015ebd
- [AMDGPU] Add new EmitDstSel field to VOPPofile. NFC. · d4385e48
  Stanislav Mekhanoshin authored Apr 15, 2021
  d4385e48
- [AMDGPU] Move LDS lowering related utility functions to a separate utils file. · 82787eb2
  hsmahesha authored Apr 16, 2021
  82787eb2
- [Hexagon] Avoid infinite loops in type legalization when lowering SETCC · 28067812
  Krzysztof Parzyszek authored Apr 15, 2021
  28067812
- [RISCV] Share RVInstIShift and RVInstIShiftW instruction format classes with the B extension. · 1656df13
  Craig Topper authored Apr 15, 2021
  1656df13
- [NewPM] Cleanup IR printing instrumentation · c8f0a7c2
  Arthur Eubanks authored Apr 14, 2021
  c8f0a7c2
- [PowerPC] Add ROP Protection Instructions for PowerPC · f28cb01b
  Stefan Pintilie authored Apr 15, 2021
  f28cb01b
- [AMDGPU] Fix large return values with amdgpu_gfx · 7842e172
  Sebastian Neubauer authored Apr 01, 2021
  7842e172
- [X86] combineCMP - fold cmpEQ/NE(TRUNC(X),0) -> cmpEQ/NE(X,0) · 9d57a77b
  Simon Pilgrim authored Apr 15, 2021
  9d57a77b
- [AArch64][NEON] Match (or (and -a b) (and (a+1) b)) => bit select · 22c017f0
  Bradley Smith authored Apr 12, 2021
  22c017f0
- [AArch64] Use type-legalization cost for code size memop cost. · acd9cc74
  Florian Hahn authored Apr 15, 2021
  acd9cc74
- [AArch64] Fix windows vararg functions with floats in the fixed args · 5144f730
  Martin Storsjö authored Apr 10, 2021
  5144f730
- [RISCV] Add a PatFrag to shorten repeated (XLenVT (VLOp GPR:$vl)) in V extension patterns. · c3f12714
  Craig Topper authored Apr 14, 2021
  c3f12714
- [AMDGPU] Disable forceful inline of non-kernel functions which use LDS. · 4973b0c4
  hsmahesha authored Apr 15, 2021
  4973b0c4
Apr 14, 2021
- [WebAssembly] Codegen for i64x2.extend_{low,high}_i32x4_{s,u} · 6a18cc23
  Thomas Lively authored Apr 14, 2021
  6a18cc23
- [WebAssembly] Codegen for f64x2.convert_low_i32x4_{s,u} · af7925b4
  Thomas Lively authored Apr 14, 2021
  af7925b4
- [AMDGPU] Factor out SelectSAddrFI() · b7ebb25e
  Stanislav Mekhanoshin authored Apr 13, 2021
  b7ebb25e
- [TTI] NFC: Change getArithmeticInstrCost to return InstructionCost · 4f42d873
  Sander de Smalen authored Apr 14, 2021
  4f42d873
- [TTI] NFC: Change getVectorInstrCost to return InstructionCost · 1af35e77
  Sander de Smalen authored Jan 27, 2021
  1af35e77
- [TTI] NFC: Change getShuffleCost to return InstructionCost · 174e8f6c
  Sander de Smalen authored Apr 14, 2021
  174e8f6c
- [TTI] NFC: Change getCFInstrCost to return InstructionCost · 14b934f8
  Sander de Smalen authored Jan 26, 2021
  14b934f8
- [TTI] NFC: Change getCallInstrCost to return InstructionCost · 596f669c
  Sander de Smalen authored Apr 14, 2021
  596f669c
- [WebAssembly] Use standard intrinsics for f32x4 and f64x2 ops · af7ab81c
  Thomas Lively authored Apr 14, 2021
  af7ab81c
- [AMDGPU] Rename "LDS lowering" pass name. · e3070db0
  hsmahesha authored Apr 14, 2021
  e3070db0
- [X86][SSE] canonicalizeShuffleWithBinOps - check for more combos of merge-able binary shuffles. · 4fbe7615
  Simon Pilgrim authored Apr 14, 2021
  4fbe7615
- [AArch64][v8.5A] Add BTI to all function starts · cca40aa8
  Pablo Barrio authored Mar 24, 2021
  cca40aa8