Commits · d70f2717263ded14554f85ef5d04df4f95b40c91 · Roger Ferrer / llvm-epi · GitLab

Dec 08, 2022
- [NFC] Port codegen PowerPC tests that invoke opt to `-passes=` syntax · d70f2717
  Roman Lebedev authored Dec 09, 2022
  
  d70f2717
- [NFC] Port codegen NVPTX tests that invoke opt to `-passes=` syntax · 62f91c12
  Roman Lebedev authored Dec 09, 2022
  
  62f91c12
- [NFC] Port codegen Generic tests that invoke opt to `-passes=` syntax · 43145d84
  Roman Lebedev authored Dec 09, 2022
  
  43145d84
- [NFC] Port codegen ARM tests that invoke opt to `-passes=` syntax · d6bd732a
  Roman Lebedev authored Dec 09, 2022
  
  d6bd732a
- [NFC] Port codegen AMDGPU tests that invoke opt to `-passes=` syntax · d4c4bd6b
  Roman Lebedev authored Dec 09, 2022
  
  d4c4bd6b
- [NFC] Port codegen AArch64 tests that invoke opt to `-passes=` syntax · 9bb01b75
  Roman Lebedev authored Dec 09, 2022
  
  9bb01b75
- [opt] Disincentivize new tests from using old pass syntax · b1a95848
  Roman Lebedev authored Dec 08, 2022
  b1a95848
- [X86] Add HasCLFLUSH pseudo-predicate (Issue #19039) · 527e453a
  Simon Pilgrim authored Dec 08, 2022
  527e453a
- [AMDGPU] Add test that spills WWM CSRs twice · 1fe65d86
  Sebastian Neubauer authored Jul 13, 2022
  1fe65d86
- [DAG] Teach isConstOrConstSplat about SPLAT_VECTORs · f4cc734a
  David Green authored Dec 08, 2022
  f4cc734a
- [test] Remove duplicate RUN lines · 51ee1074
  Bjorn Pettersson authored Dec 08, 2022
  51ee1074
- Revert "[AArch64] Select SMULL for zero extended vectors when top bit is zero" · c07a01c2
  Florian Hahn authored Dec 08, 2022
  c07a01c2
- [AArch64] Add tests for logical op with not; NFC · e121c3d3
  chenglin.bi authored Dec 08, 2022
  
  e121c3d3
- [RISCV] Add test for extract the first element from mask vector. · 3268ddd2
  Jianjian GUAN authored Dec 07, 2022
  3268ddd2
- [AArch64] Select SMULL for zero extended vectors when top bit is zero · f9e03907
  Zain Jaffal authored Dec 08, 2022
  f9e03907
- [X86] Add test masked_compressstore_isel.ll · acd8af11
  Xiang1 Zhang authored Dec 08, 2022
  
  acd8af11
- [Clang][LoongArch] Add intrinsic for csrrd, csrwr and csrxchg · 685bbe65
  gonglingqin authored Dec 08, 2022
  685bbe65
- [RISCV] Use bseti for 2048 in RISCVMatInt when Zbs is enabled. · 564e09c7
  Craig Topper authored Dec 07, 2022
  564e09c7
- [RISCV] Support F16 vectors with Zfhmin+Zvfh. · 66ff0731
  Craig Topper authored Dec 07, 2022
  66ff0731
- [PowerPC][NFC] Test case update on ppc64-acc-regalloc-bugfix.ll · 140a83e3
  Ting Wang authored Dec 07, 2022
  140a83e3
Dec 07, 2022
- [AMDGPU] Annotate the intrinsics to be default and nocallback · f6e3a89c
  Johannes Doerfert authored Oct 04, 2022
  f6e3a89c
- [amdgpu] Reimplement LDS lowering · d77ae7f2
  Jon Chesterfield authored Dec 07, 2022
  d77ae7f2
- Generate DXIL Shader hash · c861ea87
  Chris Bieneman authored Dec 05, 2022
  c861ea87
- [SPARC] Lower SELECT_CC to MOVr on 64-bit target whenever possible · f8f41c3f
  Koakuma authored Dec 07, 2022
  f8f41c3f
- Revert "[SPARC] Mark the %g0 register as constant & use it to materialize zeros" · 7806f86a
  Brad Smith authored Dec 07, 2022
  7806f86a
- AArch64: emit `fcmp ord %a, zeroinitializer` as a single fcmeq. · 6b98824a
  Tim Northover authored Nov 10, 2022
  6b98824a
- [SPARC] Mark the %g0 register as constant & use it to materialize zeros · 2c41310f
  Koakuma authored Dec 07, 2022
  2c41310f
- [AMDGPU] Enable OMod on more VOP3 instructions · bbfbec94
  Joe Nash authored Dec 02, 2022
  bbfbec94
- [GlobalISel] Add a new G_INVOKE_REGION_START instruction to fix an EH bug. · 53445f5b
  Amara Emerson authored Nov 13, 2022
  53445f5b
- [RISCV] Remove pseudos for whole register load, store, and move. · f1fd5c9b
  Craig Topper authored Dec 07, 2022
  f1fd5c9b
- [RISCV] Replace uses of hasStdExtC with COrZca. · 938d0d6d
  Craig Topper authored Dec 07, 2022
  938d0d6d
- [AMDGPU][GlobalISel] Fix legalizing image intrinsics for new types · fe42ebe4
  Mirko Brkusanin authored Dec 07, 2022
  fe42ebe4
- [AMDGPU] Add gfx11 runline to omod test. NFC · c6c4f54e
  Joe Nash authored Dec 07, 2022
  
  c6c4f54e
- [X86] Pre-commit test for pr59305 · fc16ca71
  Phoebe Wang authored Dec 08, 2022
  
  fc16ca71
- Automate tests. · f7d426b3
  Doru Bercea authored Dec 06, 2022
  
  f7d426b3
- [X86] combine-and.ll - add some 256/512-bit test coverage for D138521 · 519adee2
  Simon Pilgrim authored Dec 07, 2022
  
  519adee2
- [X86] combine-and.ll - add AVX1 test coverage · abe6dbee
  Simon Pilgrim authored Dec 07, 2022
  
  abe6dbee
- [llvm] Auto-cleanup left-over file from earlier version of this test on bots · bfe292b0
  Nico Weber authored Dec 07, 2022
  bfe292b0
- Fix a typo ll->llc in test · 3abdd9b9
  Haojian Wu authored Dec 07, 2022
  
  3abdd9b9
- Add implementation isTargetCanonicalConstantNode for hexagon. · a2215149
  Haojian Wu authored Dec 07, 2022
  a2215149