Commits · d8c6d083c954b03855700e16c81b483d2ae654d0 · Roger Ferrer / llvm-epi · GitLab

Aug 07, 2020
- [PowerPC][PCRelative] Set TLS unsupported with PC relative memops · d8c6d083
  Kamau Bridgeman authored Aug 06, 2020
  d8c6d083
- [Intrinsic] Add sshl.sat/ushl.sat, saturated shift intrinsics. · 5de6c56f
  Bevin Hansson authored Jul 16, 2020
  5de6c56f
- [DAG] GetDemandedBits - remove custom AND handling. · 66a163f3
  Simon Pilgrim authored Aug 07, 2020
  66a163f3
- [NFC][Test] Format the test with script update_llc_test_checks.py · 1ffb4683
  QingShan Zhang authored Aug 07, 2020
  
  1ffb4683
- [VE] Change to expand multiply related instructions · 63bc5d78
  Kazushi (Jam) Marukawa authored Aug 04, 2020
  63bc5d78
- [SVE][CodeGen] Fix bug with store of unpacked FP scalable vectors · 0905d9f3
  David Sherwood authored Aug 06, 2020
  0905d9f3
- [PowerPC] Implement Vector Extract Low/High Order Builtins in LLVM/Clang · cce1b0e8
  biplmish authored Aug 07, 2020
  cce1b0e8
- [PowerPC] Support constrained fp operation for setcc · 55de46f3
  QingShan Zhang authored Aug 07, 2020
  55de46f3
- [Scheduling] Create the missing dependency edges for store cluster · 3359ea62
  QingShan Zhang authored Aug 07, 2020
  3359ea62
- [StackSafety] Skip ambiguous lifetime analysis · 0b2616a8
  Vitaly Buka authored Aug 06, 2020
  0b2616a8
- [VE] Optimize trunc related instructions · f92e0d93
  Kazushi (Jam) Marukawa authored Aug 04, 2020
  f92e0d93
- GlobalISel: Implement lower for G_INSERT_VECTOR_ELT · 1ad051dd
  Matt Arsenault authored Jul 27, 2020
  
  1ad051dd
- AMDGPU/GlobalISel: Enable s_{and|or}n2_{b32|b64} patterns · 87b2af81
  Matt Arsenault authored Jul 26, 2020
  
  87b2af81
Aug 06, 2020
- [LegalTypes] Move VSELECT node creation out of WidenVSELECTAndMask and push to 2 of the 3 callers. · ffc248f3
  Craig Topper authored Aug 06, 2020
  ffc248f3
- BPF: add a SimplifyCFG IR pass during generic Scalar/IPO optimization · 87cba434
  Yonghong Song authored Aug 05, 2020
  87cba434
- GlobalISel: Implement fewerElementsVector for G_EXTRACT_VECTOR_ELT · e0020153
  Matt Arsenault authored Jul 27, 2020
  e0020153
- AMDGPU: Define raw/struct variants of buffer atomic fadd · 1a0c0944
  Matt Arsenault authored Aug 04, 2020
  1a0c0944
- AArch64/GlobalISel: Fix verifier error after selecting returnaddress · eae9c541
  Matt Arsenault authored Aug 06, 2020
  eae9c541
- AMDGPU: Fix spilling of 96-bit AGPRs · 90eb7d52
  Matt Arsenault authored Jul 31, 2020
  
  90eb7d52
- AMDGPU/GlobalISel: Start trying to handle AGPR bank · 56270d1d
  Matt Arsenault authored Jul 01, 2020
  56270d1d
- AMDGPU/GlobalISel: Handle llvm.amdgcn.ds.{fadd|fmin|fmax} · 63cdc9a4
  Matt Arsenault authored Jul 26, 2020
  63cdc9a4
- AMDGPU/GlobalISel: Try to promote to use packed saturating add/sub · 63c4be53
  Matt Arsenault authored Jul 15, 2020
  63c4be53
- [XCOFF][AIX] Put each jump table in an independent section if -ffunction-sections is specified · e5062a6c
  jasonliu authored Aug 06, 2020
  e5062a6c
- AMDGPU/GlobalISel: Implement expansion for rsq.clamp · 5a503521
  Matt Arsenault authored Jul 25, 2020
  5a503521
- AMDGPU/GlobalISel: Fix trying to widen <3 x s1> boolean ops · c015cbc6
  Matt Arsenault authored Jul 18, 2020
  
  c015cbc6
- AMDGPU/GlobalISel: Stop using G_EXTRACT in argument lowering · 28124a0a
  Matt Arsenault authored Jul 10, 2020
  28124a0a
- AMDGPU/GlobalISel: Make s16 phi legal · 37894ba6
  Matt Arsenault authored Jul 29, 2020
  37894ba6
- AMDGPU/GlobalISel: Fix assert on copy to vcc · 53162567
  Matt Arsenault authored Jul 21, 2020
  53162567
- [GlobalISel][InlineAsm] Fix matching input constraint to physreg · d893278b
  Petar Avramovic authored Aug 06, 2020
  d893278b
- [X86][SSE] Expose all memory offsets in expand load tests · 13b4db4e
  Simon Pilgrim authored Aug 05, 2020
  13b4db4e
- [SVE] Lower scalable vector mul operations. · 0d33a8ef
  Paul Walker authored Aug 05, 2020
  0d33a8ef
- [SVE] Implement lowering for fixed length vector multiplication. · 3ed59b77
  Paul Walker authored Aug 06, 2020
  3ed59b77
- [AMDGPU] add buffer_atomic_swap for float · 5ddc8b49
  Ruiling Song authored Aug 04, 2020
  5ddc8b49
- [X86] Rename mod128.ll to divmod128.ll and add test cases for sdiv/udiv/urem. · 978165bf
  Craig Topper authored Aug 05, 2020
  978165bf
- [X86] Disable copy elision in LowerMemArgument for scalarized vectors when the... · 08b2d0a9
  Craig Topper authored Aug 05, 2020
  08b2d0a9
- [X86] Add test case for PR47000. NFC · 13796d14
  Craig Topper authored Aug 05, 2020
  
  13796d14
Aug 05, 2020
- [AMDGPU] Scavenge temp reg for AGPR spill · 0bcda1a2
  Stanislav Mekhanoshin authored Aug 04, 2020
  0bcda1a2
- [Propeller]: Use a descriptive temporary symbol name for the end of the basic block. · 20a568c2
  Rahman Lavaee authored Aug 05, 2020
  20a568c2
- AMDGPU: Correct prolog SP initialization logic · ec8c172d
  Matt Arsenault authored Jul 28, 2020
  ec8c172d
- [AMDGPU] gfx1031 target · ea7d0e29
  Stanislav Mekhanoshin authored Aug 05, 2020
  ea7d0e29