Commits · db091e12b2358255d249c9f3f211f4474e2c723c · Roger Ferrer / llvm-epi · GitLab

Jul 13, 2020
- RISCV: Avoid GlobalISel build break in a future patch · db091e12
  Matt Arsenault authored Jul 13, 2020
  db091e12
- [PGO][PGSO] Add profile guided size optimization to X86ISelDAGToDAG. · fb558cca
  Hiroshi Yamauchi authored Jul 07, 2020
  fb558cca
- [PGO][PGSO] Add profile guided size optimization to the X86 LEA fixup. · 153a0b89
  Hiroshi Yamauchi authored Jul 07, 2020
  153a0b89
- [ms] [llvm-ml] Restore omitted changes requested by reviewer · 3aabfa28
  Eric Astor authored Jul 13, 2020
  
  3aabfa28
- [ms] [llvm-ml] Add support for MASM STRUCT casting field accessors: (<TYPE> PTR <value>).<field> · f08e8b6d
  Eric Astor authored Jul 13, 2020
  f08e8b6d
- [ms] [llvm-ml] Improve MASM STRUCT field accessor support · 4cdea5fa
  Eric Astor authored Jul 13, 2020
  4cdea5fa
- [ARM][MVE] Refactor option -disable-mve-tail-predication · 595270ae
  Sjoerd Meijer authored Jul 13, 2020
  595270ae
- [AMDGPU][GlobalISel] Fix subregister index for EXEC register in selectBallot. · 38998cfa
  Mirko Brkusanin authored Jul 13, 2020
  38998cfa
- [SVE] Ensure fixed length vector fptrunc operations bigger than NEON are not considered legal. · 319a97b5
  Paul Walker authored Jul 13, 2020
  319a97b5
- [AMDGPU][GlobalISel] Select llvm.amdgcn.ballot · ce23e541
  Mirko Brkusanin authored Jul 13, 2020
  ce23e541
- [PowerPC] Support constrained conversion in SPE target · b6912c87
  Qiu Chaofan authored Jul 13, 2020
  b6912c87
- [MC][RISCV] Set UseIntegratedAssembler to true · 4d5fd0ee
  Fangrui Song authored Jul 12, 2020
  4d5fd0ee
Jul 12, 2020
- [X86] Consistently use 128 as the PSHUFB/VPPERM index for zero · f8f007e3
  Craig Topper authored Jul 12, 2020
  f8f007e3
- [X86] Fix two places that appear to misuse peekThroughOneUseBitcasts · 04013a07
  Craig Topper authored Jul 12, 2020
  04013a07
- BPF: permit .maps section variables with typedef type · 152a9fef
  Yonghong Song authored Jul 11, 2020
  152a9fef
- [AVRInstPrinter] printOperand: support llvm-objdump --print-imm-hex · be9f3637
  Fangrui Song authored Jul 12, 2020
  be9f3637
Jul 11, 2020
- [AMDGPU] Move LowerSwitch pass to CodeGenPrepare. · d7a05698
  Christudasan Devadasan authored Jul 11, 2020
  d7a05698
- [X86][MMX] Optimize MMX shift intrinsics. · e6280925
  Wang, Pengfei authored Jul 10, 2020
  e6280925
- [PowerPC][MachinePipeliner] Enable pipeliner if hasInstrSchedModel · 3e3acc1c
  Jinsong Ji authored Jul 11, 2020
  3e3acc1c
- [WebAssembly] Prefer v128.const for constant splats · b59c6fca
  Thomas Lively authored Jul 10, 2020
  b59c6fca
- AMDGPU: Remove .value_type from kernel metadata · 31f4e43f
  Matt Arsenault authored Jun 29, 2020
  31f4e43f
- [X86] Add isel patterns for matching broadcast vpternlog if the ternlog and... · 122a45fb
  Craig Topper authored Jul 10, 2020
  122a45fb
Jul 10, 2020
- AArch64: Fix unused variables · 9ff310d5
  Matt Arsenault authored Jul 10, 2020
  
  9ff310d5
- [NFC] Separate Peeling Properties into its own struct (re-land after minor fix) · e541e1b7
  Sidharth Baveja authored Jul 10, 2020
  e541e1b7
- [PowerPC] Enable default support of quad precision operations · 90b1a710
  Lei Huang authored Jul 08, 2020
  90b1a710
- [ARM] Add Cortex-A78 and Cortex-X1 Support for Clang and LLVM · 954db63c
  Luke Geeson authored Jul 01, 2020
  954db63c
- [X86][SSE] Use shouldUseHorizontalOp helper to determine whether to use (F)HADD. NFCI. · 4cc26a44
  Simon Pilgrim authored Jul 10, 2020
  
  4cc26a44
- [NFC] Change isFPPredicate comparison to ignore lower bound · 69a89b54
  dstuttar authored Jul 08, 2020
  69a89b54
- [SVE] Code generation for fixed length vector truncates. · f78e6a30
  Paul Walker authored Jul 10, 2020
  f78e6a30
- [AMDGPU][GlobalISel] Fix G_AMDGPU_TBUFFER_STORE_FORMAT mapping · cf40db21
  Mirko Brkusanin authored Jul 10, 2020
  cf40db21
- [X86][AVX] Attempt to fold PACK(SHUFFLE(X,Y),SHUFFLE(X,Y)) -> SHUFFLE(PACK(X,Y)). · 77133cc1
  Simon Pilgrim authored Jul 10, 2020
  77133cc1
- [WebAssembly][NFC] Simplify vector shift lowering and add tests · 043eaa9a
  Thomas Lively authored Jul 10, 2020
  043eaa9a
- [RISCV] Refactor FeatureRVCHints to make ProcessorModel more intuitive · 04b9a46c
  Zakk Chen authored Apr 30, 2020
  04b9a46c
- [AArch64][SVE] Add lowering for llvm.fma. · 56ae2ceb
  Eli Friedman authored Jul 08, 2020
  56ae2ceb
- [PowerPC][Power10] Add Instruction definition/MC Tests for Load/Store Rightmost VSX Vector · 5ffec467
  Albion Fung authored Jul 09, 2020
  5ffec467
Jul 09, 2020
- [AMDGPU] Return restricted number of regs from TTI · 77f8f813
  Stanislav Mekhanoshin authored Jun 18, 2020
  77f8f813
- Temporarily Revert "[PowerPC] Split s34imm into two types" · ce1e4853
  Eric Christopher authored Jul 09, 2020
  ce1e4853
- [NFC][AArch64] Refactor getArgumentPopSize · 7af27b65
  Kyungwoo Lee authored Jul 09, 2020
  7af27b65
- [X86] Immediately call LowerShift from lowerBuildVectorToBitOp. · 918e6531
  Craig Topper authored Jul 09, 2020
  918e6531
- [PGO][PGSO] Add profile guided size optimization to X86 ISel Lowering. · 2c1a9006
  Hiroshi Yamauchi authored Jul 09, 2020
  
  2c1a9006