Commits · db091e12b2358255d249c9f3f211f4474e2c723c · Roger Ferrer / llvm-epi · GitLab

Jul 13, 2020
- [AMDGPU][GlobalISel] Fix subregister index for EXEC register in selectBallot. · 38998cfa
  Mirko Brkusanin authored Jul 13, 2020
  38998cfa
- [AMDGPU][GlobalISel] Select llvm.amdgcn.ballot · ce23e541
  Mirko Brkusanin authored Jul 13, 2020
  ce23e541
Jul 11, 2020
- [AMDGPU] Move LowerSwitch pass to CodeGenPrepare. · d7a05698
  Christudasan Devadasan authored Jul 11, 2020
  d7a05698
- AMDGPU: Remove .value_type from kernel metadata · 31f4e43f
  Matt Arsenault authored Jun 29, 2020
  31f4e43f
Jul 10, 2020
- [NFC] Separate Peeling Properties into its own struct (re-land after minor fix) · e541e1b7
  Sidharth Baveja authored Jul 10, 2020
  e541e1b7
- [NFC] Change isFPPredicate comparison to ignore lower bound · 69a89b54
  dstuttar authored Jul 08, 2020
  69a89b54
- [AMDGPU][GlobalISel] Fix G_AMDGPU_TBUFFER_STORE_FORMAT mapping · cf40db21
  Mirko Brkusanin authored Jul 10, 2020
  cf40db21
Jul 09, 2020
- [AMDGPU] Return restricted number of regs from TTI · 77f8f813
  Stanislav Mekhanoshin authored Jun 18, 2020
  77f8f813
Jul 08, 2020
- Revert "[NFC] Separate Peeling Properties into its own struct" · 0b39d2d7
  Nikita Popov authored Jul 08, 2020
  0b39d2d7
- [NFC] Separate Peeling Properties into its own struct · 0369dc98
  Sidharth Baveja authored Jul 08, 2020
  0369dc98
- Revert "[NFC] Separate Peeling Properties into its own struct" · 6965af43
  Anh Tuyen Tran authored Jul 08, 2020
  6965af43
- [NFC] Separate Peeling Properties into its own struct · fead250b
  Anh Tuyen Tran authored Jul 08, 2020
  fead250b
- SILoadStoreOptimizer: add support for GFX10 image instructions · 47788b97
  Jay Foad authored Jun 11, 2020
  47788b97
- [AMDGPU] Fix and simplify AMDGPULegalizerInfo::legalizeUDIV_UREM32Impl · a8816ebe
  Jay Foad authored Jun 22, 2020
  a8816ebe
- [AMDGPU] Fix and simplify AMDGPUTargetLowering::LowerUDIVREM · ecac951b
  Jay Foad authored Jun 22, 2020
  ecac951b
- [AMDGPU] Fix and simplify AMDGPUCodeGenPrepare::expandDivRem32 · f4bd01c1
  Jay Foad authored Jun 22, 2020
  f4bd01c1
Jul 07, 2020
- GlobalISel: Handle EVT argument lowering correctly · 23157f3b
  Matt Arsenault authored Jul 07, 2020
  23157f3b
- AMDGPU/GlobalISel: Fix skipping unused kernel arguments · 42bb4814
  Matt Arsenault authored Jul 07, 2020
  42bb4814
- [AMDGPU] Update isFMAFasterThanFMulAndFAdd assumptions · 560292fa
  Carl Ritson authored Jul 07, 2020
  560292fa
Jul 06, 2020
- [AMDGPU] Tweak getTypeLegalizationCost() · f7a7efbf
  Stanislav Mekhanoshin authored Jul 02, 2020
  f7a7efbf
- AMDGPU/GlobalISel: Add types to special inputs · f25d020c
  Matt Arsenault authored Jul 05, 2020
  f25d020c
- DomTree: Remove getRoots() accessor · dfcc68c5
  Nicolai Hähnle authored May 18, 2020
  dfcc68c5
- AMDGPU: Don't ignore carry out user when expanding add_co_pseudo · c19c153e
  Matt Arsenault authored Jun 19, 2020
  c19c153e
- AMDGPU/GlobalISel: Don't emit code for unused kernel arguments · a5b9ad7e
  Matt Arsenault authored Jul 05, 2020
  
  a5b9ad7e
- AMDGPU: Fix fixed ABI SGPR arguments · 7b76a5c8
  Matt Arsenault authored Jul 05, 2020
  7b76a5c8
Jul 03, 2020
- [AMDGPU] Don't combine DPP if DPP register is used more than once per instruction · bb69ca82
  vpykhtin authored Jun 25, 2020
  bb69ca82
- [Alignment][NFC] Use proper getter to retrieve alignment from ConstantInt and ConstantSDNode · 87e2751c
  Guillaume Chatelet authored Jul 03, 2020
  87e2751c
- [NFC] Use ADT/Bitfields in Instructions · 3587c9c4
  Guillaume Chatelet authored Jul 03, 2020
  3587c9c4
- [AMDGPU] Insert PS early exit at end of control flow · 42ca2070
  Carl Ritson authored Jul 03, 2020
  42ca2070
- Revert "[AMDGPU] Insert PS early exit at end of control flow" · 7ec6927b
  Carl Ritson authored Jul 03, 2020
  7ec6927b
- [AMDGPU] Insert PS early exit at end of control flow · 2bfcacf0
  Carl Ritson authored Jul 03, 2020
  2bfcacf0
- [AMDGPU] Unify early PS termination blocks · a3daa3f7
  Carl Ritson authored Jul 03, 2020
  a3daa3f7
Jul 02, 2020
- [AMDGPU][CODEGEN] Added support of new inline assembler constraints · 1c9d6810
  Dmitry Preobrazhensky authored Jul 02, 2020
  1c9d6810
- [AMDGPU] Control num waves per EU for implicit work-group size · e1a31f52
  Pushpinder Singh authored Jun 17, 2020
  e1a31f52
- AMDGPU: Set more mov flags on V_ACCVGPR_{READ|WRITE}_B32 · d2e74fad
  Matt Arsenault authored Jul 01, 2020
  d2e74fad
- [AMDGPU] Limit promote alloca to vector with VGPR budget · 54e2dc75
  Stanislav Mekhanoshin authored Jul 01, 2020
  54e2dc75
Jul 01, 2020
- AMDGPU: Support commuting register and global operand · 14fe4607
  Matt Arsenault authored Jul 01, 2020
  
  14fe4607
- AMDGPU: Fix handling of target flags when commuting instruction · a21544ad
  Matt Arsenault authored Jul 01, 2020
  a21544ad
- AMDGPU: Clear subreg when folding immediate copies · 16ea23ff
  Matt Arsenault authored Jun 30, 2020
  16ea23ff
- Change the INLINEASM_BR MachineInstr to be a non-terminating instruction. · 4b0aa572
  James Y Knight authored May 15, 2020
  4b0aa572