Differential Revision: https://reviews.llvm.org/D54978

llvm-svn: 356929

I think this is correct, but may not necessarily be the correct fix
for the assertion I'm really trying to solve. If a scheduling region
was found that only has dbg_value instructions, the RegPressure
tracker would end up in an inconsistent state because it would skip
over any debug instructions and point to an instruction outside of the
scheduling region. It may still be possible for this to happen if
there are some real schedulable instructions between dbg_values, but I
haven't managed to break this.

The testcase is extremely sensitive and I'm not sure how to make it
more resistent to future scheduler changes that would avoid stressing
this situation.

llvm-svn: 356926

llvm-svn: 356924

This seems to already be done, but wasn't marked.

llvm-svn: 356922

llvm-objcopy previously knew nothing about data in segments that wasn't
covered by section headers, meaning that it wrote zeroes instead of what
was there. As it is possible for this data to be useful to the loader,
this patch causes llvm-objcopy to start preserving this data. Data in
sections that are explicitly removed continues to be written as zeroes.

This fixes https://bugs.llvm.org/show_bug.cgi?id=41005.

Reviewed by: jakehehrlich, rupprecht

Differential Revision: https://reviews.llvm.org/D59483

llvm-svn: 356919

Differential Revision: https://reviews.llvm.org/D59738

llvm-svn: 356915

The AVX1 lowering is poor.

llvm-svn: 356914

Remove attempts to commute non-Instructions to the LHS - the codegen changes appear to rely on chance more than anything else and also have a tendency to fight existing instcombine canonicalization which moves constants to the RHS of commutable binary ops.

This is prep work towards:
(a) reusing reorderInputsAccordingToOpcode for alt-shuffles and removing the similar reorderAltShuffleOperands
(b) improving reordering to optimized cases with commutable and non-commutable instructions to still find splat/consecutive ops.

Differential Revision: https://reviews.llvm.org/D59738

llvm-svn: 356913

Commited from wrong directory...

llvm-svn: 356907

Differential Revision: https://reviews.llvm.org/D59590

llvm-svn: 356905

functions should begin with lower case letters. NFC.

llvm-svn: 356901

Remove the IR part from test/CodeGen/X86/regalloc-copy-hints.mir (added by
r355854).

To make the test remain functional, the parts of the MBB names referring to
BB names have been removed, as well as all machine memory operands.

llvm-svn: 356899

[DebugInfo] IntelJitEventListener follow up for "add SectionedAddress ..."

Following r354972 the Intel JIT Listener would not report line table
information because the section indices did not match. There was
a similar issue with the PerfJitEventListener. This change performs
the section index lookup when building the object address used to
query the line table information.

Differential Revision: https://reviews.llvm.org/D59490

llvm-svn: 356895

Summary:
Move ClangTidyCheck to a separate header/.cpp
Switch checks to #include "ClangTidyCheck.h"
Mention ClangTidyCheck.h in the docs

Reviewers: hokein, gribozavr, aaron.ballman

Reviewed By: hokein

Subscribers: mgorny, javed.absar, xazax.hun, arphaman, jdoerfert, llvm-commits, cfe-commits

Tags: #clang, #llvm

Differential Revision: https://reviews.llvm.org/D59714

llvm-svn: 356890

The idea of the patch is about to move out the code to a new
helper static functions (to reduce the size of 'handleArgs' and to
isolate the parts of it's logic).

Differential revision: https://reviews.llvm.org/D59762

llvm-svn: 356889

Move selectCopy into MipsInstructionSelector class.
Select copy for arguments from FPRBRegBank for MIPS32.

Differential Revision: https://reviews.llvm.org/D59644

llvm-svn: 356886

- Make introduction a bit shorter
- Add a `git clone` step to Quick start
- Put command to run first in each of the Quick start steps
- Use ``code`` instead of `label` throughout; this is .rst not .md

Differential Revision: https://reviews.llvm.org/D59600

llvm-svn: 356885

The zip is small, and it's a bit less code this way.
No intended behavior change.

Differential Revision: https://reviews.llvm.org/D59677

llvm-svn: 356884

Add floating point register bank for MIPS32.
Implement getRegBankFromRegClass for float register classes.

Differential Revision: https://reviews.llvm.org/D59643

llvm-svn: 356883

Lower float and double arguments in registers for MIPS32.
When float/double argument is passed through gpr registers
select appropriate move instruction.

Differential Revision: https://reviews.llvm.org/D59642

llvm-svn: 356882

Summary:
Currently, llvm-readobj can dump symbol version sections only in LLVM style. In this patch, I would like to separate these dumpers into GNU style and 
LLVM style for future implementation.

Reviewers: grimar, jhenderson, mattd, rupprecht

Reviewed By: jhenderson, rupprecht

Subscribers: ormris, dyung, RKSimon, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D59186

llvm-svn: 356881

llvm-svn: 356875

Moving this to base class TargetTransformInfoImplCRTPBase allows static_cast to
a subtarget so that calls to e.g. getMemcpyCost actually go the overridden
functions.

Differential revision: https://reviews.llvm.org/D59706

llvm-svn: 356873

We currently use only VLDR/VSTR for all 64-bit loads/stores, so the
memory operands must be word-aligned. Mark aligned operations as legal
and narrow non-aligned ones to 32 bits.

While we're here, also mark non-power-of-2 loads/stores as unsupported.

llvm-svn: 356872

[X86] Update some of the getMachineNode calls from X86ISelDAGToDAG to also include a VT for a EFLAGS result.

This makes the nodes consistent with how they would be emitted from the isel
table.

llvm-svn: 356870

[X86] When selecting (x << C1) op C2 as (x op (C2>>C1)) << C1, use the operation VT for the target constant.

Normally when the nodes we use here(AND32ri8 for example) are selected their
immediates are just converted from ConstantSDNode to TargetConstantSDNode
without changing VT from the original operation VT. So we should still be
emitting them with the operation VT.

Theoretically this could expose more accurate opportunities for CSE.

llvm-svn: 356869

We were using this to create an AND32ri8 node from a 64-bit and, but that node
normally still uses a 32-bit immediate. So we should just truncate the existing
immediate to i32. We already verified it has the same value in bits 31:7.

llvm-svn: 356868

llvm-svn: 356867

Revert r356688 "[X86] Don't avoid folding multiple use sign extended 8-bit immediate into instructions under optsize."

Looking back over how the one use optimization works, I don't think this is the right way to fix this.

llvm-svn: 356866

Enable SSE41 ZERO_EXTEND_VECTOR_INREG shuffle combines - for the PMOVZX(PSHUFD(V)) -> UNPCKH(V,0) pattern we reduce the shuffles (port5-bottleneck on Intel) at the expense of creating a zero (pxor v,v) and an extra register move - which is a good trade off as these are pretty cheap and in most cases it doesn't increase register pressure.

This also exposed a missed opportunity to use combine to ZERO_EXTEND_VECTOR_INREG with folded loads - even if we're in the float domain.

llvm-svn: 356864

Class `RegionInfo` was `SortUnitInfo` before, so the variables were
named `SUI`. Now the class name is `RegionInfo`, so this renames `SUI`
to `RI`, matching the class name.

llvm-svn: 356861

An i16 bswap can be implemented with an i16 rotate by 8. We previously emitted
a shift and OR sequence that DAG combine should be able to turn back into
rotate. But we might as well go there directly. If rotate isn't legal,
LegalizeDAG should further legalize it to either the opposite rotate, or the
shift and OR pattern.

I don't know of any way to get the existing DAG combine reliance to fail. So
I don't know any way to add new tests for this that wouldn't have worked
previously.

llvm-svn: 356860

Pre-commit for D59363 (Add icmp UNDEF handling to SelectionDAG::FoldSetCC)

Approved by @spatel (Sanjay Patel)

llvm-svn: 356859

Just enable this for AVX for now as SSE41 introduces extra register moves for the PMOVZX(PSHUFD(V)) -> UNPCKH(V,0) pattern (but otherwise helps reduce port5 usage on Intel targets).

Only AVX support is required for PR40685 as the issue is due to 8i8->8i32 zext shuffle leftovers.

llvm-svn: 356858

This is extracted from D59696 as suggested in the review. It is
preparation for making the DominatorTree a member variable.

llvm-svn: 356857

Fix: r356853 + set AddressAlign to 4 in 
Inputs/compress-debug-sections.yaml for the new group section introduced.

Original commit message:

Currently, llvm-objcopy incorrectly handles compression and decompression of the
sections from COMDAT groups, because we do not implement the
replaceSectionReferences for this type of the sections.

The patch does that.

Differential revision: https://reviews.llvm.org/D59638

llvm-svn: 356856

This is yet another step towards solving PR14613:
https://bugs.llvm.org/show_bug.cgi?id=14613

uaddsat X, Y --> (X >u (X + Y)) ? -1 : X + Y
usubsat X, Y --> (X >u Y) ? X - Y : 0

We can't count on a sane vector ISA, so override the default (umin/umax)
expansion of unsigned add/sub saturate in cases where we do not have umin/umax.

Differential Revision: https://reviews.llvm.org/D59006

llvm-svn: 356855

Remove the I.getOperand() calls from inside shouldReorderOperands - reorderInputsAccordingToOpcode should handle the creation of the operand lists and shouldReorderOperands should just check to see whether the i'th element should be commuted.

llvm-svn: 356854

This patch fixes the reason of ubsan failure (UB detected) 
happened after landing the D59638 (I had to revert it).
http://lab.llvm.org:8011/builders/sanitizer-x86_64-linux-bootstrap-ubsan/builds/11760/steps/check-llvm%20ubsan/logs/stdio)

Problem is the following. Our implementation of GroupSection assumes that
its address is 4 bytes aligned when writes it:

template <class ELFT>
void ELFSectionWriter<ELFT>::visit(const GroupSection &Sec) {
  ELF::Elf32_Word *Buf =
      reinterpret_cast<ELF::Elf32_Word *>(Out.getBufferStart() + Sec.Offset);
...

But the test case for D59638 did not set AddressAlign in YAML. So address was
not 4 bytes aligned since Sec.Offset was odd. That triggered the issue.

This patch teaches llvm-objcopy to report an error for such sections (which should
not met in reality), what is better than having UB.

Differential revision: https://reviews.llvm.org/D59695

llvm-svn: 356853

This adds ConstantRange::getFull(BitWidth) and
ConstantRange::getEmpty(BitWidth) named constructors as more readable
alternatives to the current ConstantRange(BitWidth, /* full */ false)
and similar. Additionally private getFull() and getEmpty() member
functions are added which return a full/empty range with the same bit
width -- these are commonly needed inside ConstantRange.cpp.

The IsFullSet argument in the ConstantRange(BitWidth, IsFullSet)
constructor is now mandatory for the few usages that still make use of it.

Differential Revision: https://reviews.llvm.org/D59716

llvm-svn: 356852