Commits · dd13be0bccc888926cb5a5e81912b89b28142669 · Roger Ferrer / llvm-epi · GitLab

Aug 19, 2015
- [x86] enable machine combiner reassociations for scalar double-precision min/max · 9e5927fd
  Sanjay Patel authored Aug 19, 2015
  9e5927fd
- [x86] enable machine combiner reassociations for scalar single-precision maximums · 4e3ee1e5
  Sanjay Patel authored Aug 19, 2015
  4e3ee1e5
- [AArch64][FastISel] Don't fold shifts with UB. · b12248e9
  Juergen Ributzka authored Aug 19, 2015
  b12248e9
- [X86] Emit more efficient >= comparisons against 0 · f25fe647
  David Majnemer authored Aug 19, 2015
  f25fe647
- [WebAssembly] Use the default alignment for SIMD types. · dde8dce6
  Dan Gohman authored Aug 19, 2015
  dde8dce6
- [Sparc]: asm-only support for the ldstub instruction. · 2362b69d
  Douglas Katzman authored Aug 19, 2015
  2362b69d
- Temporary fix for the self-host failures introduced by rL244921. · 5f1cea41
  Nemanja Ivanovic authored Aug 19, 2015
  5f1cea41
- [PeepholeOptimizer] Look through PHIs to find additional register sources · 27fd0692
  Bruno Cardoso Lopes authored Aug 19, 2015
  27fd0692
- [SPARC] Enable writing to floating-point-state register. · e5485c65
  Douglas Katzman authored Aug 19, 2015
  e5485c65
- [AArch64] Improve short-form diags on long-form Match_InvalidOperand. · 9e00ec61
  Ahmed Bougacha authored Aug 19, 2015
  9e00ec61
- Revert "[AArch64] Simplify/refactor code to ease code review. NFC." · eb552e83
  Renato Golin authored Aug 19, 2015
  eb552e83
- x32. Fixes a bug in x32 exception handling. · 55817ee6
  Derek Schuff authored Aug 19, 2015
  55817ee6
- x32. Fixes jmp %reg in x32 · 5ab87edb
  JF Bastien authored Aug 19, 2015
  5ab87edb
- [Sparc] Rename LoadASR and StoreASR from r245360 to *ASI, as was intended. · 3b0fd753
  James Y Knight authored Aug 19, 2015
  3b0fd753
- Revert "[PeepholeOptimizer] Look through PHIs to find additional register sources" · 61009142
  Bruno Cardoso Lopes authored Aug 19, 2015
  61009142
- [SPARC] Fix BooleanContents, so that select of a trunc doesn't · d966fb6f
  James Y Knight authored Aug 19, 2015
  d966fb6f
- [AArch64] Simplify/refactor code to ease code review. NFC. · 494abf1a
  Chad Rosier authored Aug 19, 2015
  494abf1a
- [PeepholeOptimizer] Look through PHIs to find additional register sources · 0a1c1266
  Bruno Cardoso Lopes authored Aug 19, 2015
  0a1c1266
- [ARM] Add instruction selection patterns for vmin/vmax · ad1b19fc
  Silviu Baranga authored Aug 19, 2015
  ad1b19fc
- Map %fprs to %asr6 in the Sparc assembler parser. · 7d180c59
  Joerg Sonnenberger authored Aug 19, 2015
  7d180c59
- Revert "[X86] Widen the 'AND' mask if doing so shrinks the encoding size" · 85508e80
  Tobias Grosser authored Aug 19, 2015
  85508e80
- [X86] Do not lower scalar sdiv/udiv to a shifts + mul sequence when optimizing for minsize · 9fe42604
  Michael Kuperstein authored Aug 19, 2015
  9fe42604
- [TLI] Refactor "is integer division cheap" queries. · dcdab4cd
  Michael Kuperstein authored Aug 19, 2015
  dcdab4cd
- MIR Serialization: Serialize the operand's bit mask target flags. · f3630113
  Alex Lorenz authored Aug 18, 2015
  f3630113
- use TLI.allowsMemoryAccess() to check if memory accesses are fast; NFCI · 5c55fbc5
  Sanjay Patel authored Aug 18, 2015
  5c55fbc5
Aug 18, 2015
- Load/store instructions for floating points with address space require SparcV9. · b0ce8747
  Joerg Sonnenberger authored Aug 18, 2015
  b0ce8747
- [WinEH] Calculate state numbers for the new EH representation · 0ad363ee
  David Majnemer authored Aug 18, 2015
  0ad363ee
- MachineRegisterInfo: Introduce isPhysRegUsed() · d55bcf26
  Matthias Braun authored Aug 18, 2015
  d55bcf26
- use minSize wrapper; NFCI · 1cd6d88e
  Sanjay Patel authored Aug 18, 2015
  1cd6d88e
- [AArch64] Simplify the logic for computing in bounds offset. NFC. · 3dd0e942
  Chad Rosier authored Aug 18, 2015
  3dd0e942
- [mips] Expand JAL instructions when PIC is enabled. · 63f4a5dc
  Daniel Sanders authored Aug 18, 2015
  63f4a5dc
- [mips][microMIPS] Implement DDIV, DMOD, DDIVU and DMODU instructions · 2fe8466f
  Zoran Jovanovic authored Aug 18, 2015
  2fe8466f
- [mips][microMIPS] Implement SW and SWE instructions · a6593ff6
  Zoran Jovanovic authored Aug 18, 2015
  a6593ff6
- [mips] Make the MipsAsmParser capable of knowing whether PIC mode is enabled or not. · a6994440
  Daniel Sanders authored Aug 18, 2015
  a6994440
- [mips] Correct -Woverflow warning in r245208 without changing signedness of the constant. · f1ae367a
  Daniel Sanders authored Aug 18, 2015
  f1ae367a
- Align SP adjustment in function getSPAdjust · f66d3844
  Guozhi Wei authored Aug 17, 2015
  f66d3844
Aug 17, 2015
- [SPARC]: recognize '.' as the start of an assembler expression. · 685a7d1a
  Douglas Katzman authored Aug 17, 2015
  685a7d1a
- [ARM] Fix crash when targetting CPU without NEON · 974838f2
  James Molloy authored Aug 17, 2015
  974838f2
- [CostModel][AArch64] Increase cost of vector insert element and add missing cast costs · b322aa6f
  Silviu Baranga authored Aug 17, 2015
  b322aa6f
- [CostModel][ARM] Increase cost of insert/extract operations · d5ac2693
  Silviu Baranga authored Aug 17, 2015
  d5ac2693