Commits · def7cfb7ffd40691f903287a060f4405bab56d1a · Roger Ferrer / llvm-epi · GitLab

Nov 22, 2020
- [InstCombine] Use is_contained (NFC) · def7cfb7
  Kazu Hirata authored Nov 21, 2020
  
  def7cfb7
Nov 21, 2020
- [BasicAA] Remove unnecessary sextOrSelf (NFC) · ded59288
  Nikita Popov authored Nov 21, 2020
  ded59288
- [BasicAA] Return DecomposedGEP (NFC) · 0d114f56
  Nikita Popov authored Nov 21, 2020
  0d114f56
- [BasicAA] Remove some intermediate variables (NFC) · f4412c5a
  Nikita Popov authored Nov 21, 2020
  f4412c5a
- [BasicAA] Remove stale FIXME (NFC) · 913a99c4
  Nikita Popov authored Nov 21, 2020
  913a99c4
- [X86] Include %rip for 32-bit RIP-relative relocs for x32 · 4629afa1
  Harald van Dijk authored Nov 21, 2020
  4629afa1
- [VE][NFC] Modify function order and simplify comments · 4a1d230f
  Kazushi (Jam) Marukawa authored Nov 19, 2020
  
  4a1d230f
- [VE] Correct types of return/argument values for getAdjustedFrameSize() · 02b2bcd9
  Kazushi (Jam) Marukawa authored Nov 15, 2020
  02b2bcd9
- OpaquePtr: Make byval/sret types mandatory · 41083267
  Matt Arsenault authored Nov 20, 2020
  
  41083267
- AMDGPU: Fix counting kernel arguments towards register usage · 79f75468
  Matt Arsenault authored Oct 20, 2020
  79f75468
- [Analysis] Use llvm::is_contained (NFC) · 226beb49
  Kazu Hirata authored Nov 20, 2020
  
  226beb49
- Verifier: Fix assert when verifying non-pointer byval or preallocated · 650fbd56
  Matt Arsenault authored Nov 20, 2020
  650fbd56
Nov 20, 2020
- [AArch64][GlobalISel] Make G_EXTRACT_VECTOR_ELT of <2 x p0> legal. · c58df888
  Amara Emerson authored Nov 20, 2020
  c58df888
- [SLP][NFC]Fix assert condition in newTreeEntry, NFC. · 0b420d67
  Alexey Bataev authored Nov 20, 2020
  
  0b420d67
- [RISCV] Put RV32 before RV64 in the ValueTypeByHwMode and RegInfoByHwMode... · 9211da42
  Craig Topper authored Nov 20, 2020
  9211da42
- [RISCV] Remove RV32 HwMode. Use DefaultMode for RV32 · 77e25b5b
  Craig Topper authored Nov 20, 2020
  77e25b5b
- [CSSPGO] MIR target-independent pseudo instruction for pseudo-probe intrinsic · d0e42037
  Hongtao Yu authored Sep 10, 2020
  d0e42037
- [RISCV] Custom type legalize i32 bswap/bitreverse to GREVIW on RV64 with Zbp extension · 6a1d8b91
  Craig Topper authored Nov 20, 2020
  6a1d8b91
- [CSSPGO] IR intrinsic for pseudo-probe block instrumentation · f3c44569
  Hongtao Yu authored Nov 18, 2020
  f3c44569
- [RISCV] Add RISCVISD::ROLW/RORW use those for custom legalizing i32 rotl/rotr on RV64IZbb. · 78767b7f
  Craig Topper authored Nov 20, 2020
  78767b7f
- [X86][AVX] LowerADDSAT_SUBSAT - avoid X86ISD::BLENDV in UADDSAT/USUBSAT v8i32/v4i64 lowering · 0341029b
  Simon Pilgrim authored Nov 20, 2020
  0341029b
- [SelectionDAG][X86][PowerPC][Mips] Replace the default implementation of... · a7eae62a
  Craig Topper authored Nov 20, 2020
  a7eae62a
- [Hexagon][NewPM] Port -hexagon-loop-idiom and add to pipeline · ac7419bb
  Arthur Eubanks authored Nov 19, 2020
  ac7419bb
- [DeadMachineInstrctionElim] Post order visit all blocks and Iteratively run... · 1cd19fc5
  Andrew Wei authored Nov 21, 2020
  1cd19fc5
- [X86][SSE] LowerADDSAT_SUBSAT - avoid X86ISD::BLENDV in UADDSAT/USUBSAT custom lowering · 09a081f2
  Simon Pilgrim authored Nov 20, 2020
  09a081f2
- [AMDGPU] Set the default globals address space to 1 · 51e09e1d
  Alex Richardson authored Jul 22, 2020
  51e09e1d
- Add a default address space for globals to DataLayout · 3bc41575
  Alex Richardson authored Nov 20, 2020
  3bc41575
- Reland: Expand existing loopsink testing to also test loopsinking using new... · 7f6360cd
  Jamie Schmeiser authored Nov 20, 2020
  7f6360cd
- [NFC intended] Refactor the code for printChanged for reuse and to facilitate... · 621efa6a
  Jamie Schmeiser authored Nov 20, 2020
  621efa6a
- [AArch64] Enable post RA scheduler for Cortex-R82 · 412237dc
  Sjoerd Meijer authored Nov 20, 2020
  412237dc
- [ARM] Disable WLSTP loops · f08c37da
  David Green authored Nov 20, 2020
  f08c37da
- [AArch64] Out-of-line atomics (-moutline-atomics) implementation. · 4d7df43f
  Pavel Iliin authored Nov 19, 2020
  4d7df43f
- [VE] Change threshold for jump table generation · 42389f1e
  Kazushi (Jam) Marukawa authored Nov 19, 2020
  42389f1e
- [AMDGPU] Implement flat scratch init for pal · 7a18bdb3
  Sebastian Neubauer authored Oct 15, 2020
  7a18bdb3
- [X86] Add support for vex, vex2, vex3, and evex for MASM · 776f92e0
  Liu, Chen3 authored Oct 30, 2020
  776f92e0
- [lib/Object] - Generalize the RelocationResolver API. · 9a99d23a
  Georgii Rymar authored Nov 12, 2020
  9a99d23a
- [PGO] Make -disable-preinline work with NPM · b7743604
  Arthur Eubanks authored Nov 19, 2020
  b7743604
- [CodeGen] Use llvm::is_contained (NFC) · 2583d8eb
  Kazu Hirata authored Nov 19, 2020
  
  2583d8eb
- [PowerPC] Allow a '%' prefix for registers in CFI directives · b2f66307
  Bill Wendling authored Nov 18, 2020
  b2f66307
- Port -lower-matrix-intrinsics-minimal to NPM · 513d165b
  Arthur Eubanks authored Nov 17, 2020
  513d165b