Commits · e03ba2198dbb6b053f600c798770593d8f69055d · Roger Ferrer / llvm-epi · GitLab

Oct 31, 2020
- [AVR] Improve inline rotate/shift expansions · e03ba219
  Ayke van Laethem authored Aug 23, 2020
  e03ba219
- [X86] Support Intel avxvnni · 756f5978
  Liu, Chen3 authored Oct 30, 2020
  756f5978
- [WebAssembly] Prototype i64x2.bitmask · a787e097
  Thomas Lively authored Oct 30, 2020
  a787e097
- [WebAssembly] Prototype i64x2.eq · 0a512a55
  Thomas Lively authored Oct 30, 2020
  0a512a55
Oct 30, 2020
- [WebAssembly] Prototype i64x2.widen_{low,high}_i32x4_{s,u} · 1cb0b566
  Thomas Lively authored Oct 30, 2020
  1cb0b566
- hwasan: Support for outlined checks in the Linux kernel. · 3d049bce
  Peter Collingbourne authored Oct 27, 2020
  3d049bce
- [Legalize] Add legalizations for VECREDUCE_SEQ_FADD · dda1e74b
  Cameron McInally authored Oct 30, 2020
  dda1e74b
- AArch64: Use SBFX instead of UBFX to extract address granule in outlined HWASan checks. · c9b1a2b4
  Peter Collingbourne authored Oct 27, 2020
  c9b1a2b4
- AArch64: Switch to x20 as the shadow base register for outlined HWASan checks. · 3859fc65
  Peter Collingbourne authored Oct 27, 2020
  3859fc65
- [AMDGPU] Refactor and extend elf-header-flags-mach tests · 13a56ca5
  Scott Linder authored Oct 30, 2020
  13a56ca5
- [VE][NFC] move scalar tests to Scalar/ · 1943b7f1
  Simon Moll authored Oct 30, 2020
  1943b7f1
- AMDGPU: Fix missing writelane cases to skip with exec=0 · 790f5771
  Matt Arsenault authored Oct 16, 2020
  
  790f5771
- [ARM] Update target triple in tests. NFC · 87c27e67
  David Green authored Oct 30, 2020
  
  87c27e67
- [stack-clash] Fix probing of dynamic alloca · 0f60bcc3
  serge-sans-paille authored Oct 27, 2020
  0f60bcc3
- [SVE] Add fatal error for unnamed SVE variadic arguments · cea69fa4
  David Sherwood authored Oct 27, 2020
  cea69fa4
- [ARM] Match MVE vqdmulh · d14db8c8
  David Green authored Oct 30, 2020
  d14db8c8
- [ARM] Additional MVE VQDMULH tests. NFC · dba33258
  David Green authored Oct 30, 2020
  
  dba33258
- [Hexagon] Handle additional shuffles that can be made perfect · db60e640
  Krzysztof Parzyszek authored Oct 29, 2020
  
  db60e640
Oct 29, 2020
- [RISCV] Improve worklist management in the DAG combine for SLLW/SRLW/SRAW · 74b07829
  Craig Topper authored Oct 29, 2020
  74b07829
- [RISCV] Add test case for D90339 · 541effe0
  Craig Topper authored Oct 29, 2020
  
  541effe0
- [WebAssembly] Remove unused FileCheck test prefixes · 6214be3a
  Thomas Lively authored Oct 29, 2020
  6214be3a
- [SDAG] Fix neutral value for vecreduce_fadd · a5f17292
  Nikita Popov authored Oct 29, 2020
  a5f17292
- [CodeGen] Fix neutral value of vecreduce fadd in tests (NFC) · fa48ff3f
  Nikita Popov authored Oct 29, 2020
  fa48ff3f
- [WebAssembly] Implement SIMD signselect instructions · be6f5079
  Thomas Lively authored Oct 29, 2020
  be6f5079
- [X86] Add PR46393 test case · 93ebefb9
  Simon Pilgrim authored Oct 29, 2020
  
  93ebefb9
- [AMDGPU] Use pseudo instructions for readlane/writelane · 58de4b20
  Jay Foad authored Oct 29, 2020
  58de4b20
- [ARM] Fix IT block generation after Thumb2SizeReduce with -Oz · eb9fe24e
  Nicholas Guy authored Oct 29, 2020
  eb9fe24e
- [ARM] Add IT block generation test · 7b8de9fc
  Nicholas Guy authored Oct 29, 2020
  7b8de9fc
- [AMDGPU] Remove gds operand from ds_gws_* MachineInstrs · 7a79921e
  Jay Foad authored Oct 29, 2020
  7a79921e
- [MIR] Fix out of bounds access in MIRPrinter. · b3cdaef5
  dfukalov authored Oct 27, 2020
  b3cdaef5
- [InterleaveAccess] Recognise Interleave loads through binary operations · a4b6b1e1
  David Green authored Oct 29, 2020
  a4b6b1e1
- [AMDGPU] Add Reset function to GCNHazardRecognizer · de518673
  Austin Kerbow authored Oct 28, 2020
  de518673
Oct 28, 2020
- [AMDGPU] Allow some modifiers on VOP3B instructions · 5b91a6a8
  Jay Foad authored Oct 27, 2020
  5b91a6a8
- [AArch64] Improve lowering of insert_vector_elt with 0.0 consts. · 772aaa60
  Florian Hahn authored Oct 28, 2020
  772aaa60
- [AMDGPU] Fix inserting combined s_nop in bundles · 8b127a86
  Austin Kerbow authored Oct 28, 2020
  8b127a86
- [test] Make bt_order_by_weight in switch.ll more robust · 3b2256a4
  Arthur Eubanks authored Oct 27, 2020
  3b2256a4
- [AArch64] Use DUP for BUILD_VECTOR with few different elements. · ba78cae2
  Florian Hahn authored Oct 28, 2020
  ba78cae2
- [GISel]: Few InsertVecElt combines · bed83940
  Aditya Nandakumar authored Oct 28, 2020
  bed83940
- [WebAssembly] Prototype extending multiplication SIMD instructions · 31e94455
  Thomas Lively authored Oct 28, 2020
  31e94455
- RegAlloc: Clear isSSA · b9c21d43
  Matt Arsenault authored Oct 23, 2020
  b9c21d43