Commits · e1dd212c874c2ff01b72e9e60db6dbded9e2e6d1 · Roger Ferrer / llvm-epi · GitLab

Jul 28, 2020
- [X86] Remove disabled miscompiling X86CondBrFolding pass · e1dd212c
  Roman Lebedev authored Jul 28, 2020
  e1dd212c
- [DAG] isSplatValue - add support for TRUNCATE/SIGN_EXTEND/ZERO_EXTEND · b4b6e774
  Simon Pilgrim authored Jul 28, 2020
  b4b6e774
- [X86][XOP] Shuffle v16i8 using VPPERM(X,Y) instead of OR(PSHUFB(X),PSHUFB(Y)) · 4838cd46
  Simon Pilgrim authored Jul 28, 2020
  
  4838cd46
- [AMDGPU] Spill CSR VGPR which is reserved for SGPR spills · adeeac9d
  Austin Kerbow authored Jul 13, 2020
  adeeac9d
- [ARM][MVE] Teach MVEGatherScatterLowering to merge successive getelementpointers · 0c64233b
  Anna Welker authored Jul 28, 2020
  0c64233b
- GlobalISel: Translate llvm.convert.{to|from}.fp16 intrinsics · 97b5fb78
  Matt Arsenault authored Jul 25, 2020
  97b5fb78
- AMDGPU/GlobalISel: Use clamp modifier for [us]addsat/[us]subsat · a4edc046
  Matt Arsenault authored Jul 12, 2020
  a4edc046
- [AArch64][SVE] Fix epilogue for SVE when the stack is realigned. · cda2eb3a
  Sander de Smalen authored Jul 28, 2020
  cda2eb3a
- [AArch64][SVE] Don't align the last SVE callee save. · 26b4ef36
  Sander de Smalen authored Jul 27, 2020
  26b4ef36
- [AArch64][SVE] Don't support fixedStack for SVE objects. · 54492a58
  Sander de Smalen authored Jul 27, 2020
  54492a58
- Re-land "[PowerPC] Remove QPX/A2Q BGQ/BGP CNK support" · d28f8672
  Jinsong Ji authored Jul 28, 2020
  d28f8672
- ARM: make Thumb1 instructions non-flag-setting in IT block. · 39108f4c
  Tim Northover authored Jul 27, 2020
  39108f4c
- [X86][SSE] Attempt to match OP(SHUFFLE(X,Y),SHUFFLE(X,Y)) -> SHUFFLE(HOP(X,Y)) · 18211177
  Simon Pilgrim authored Jul 28, 2020
  18211177
- [PowerPC] test case for adding dq form to isLegalAddressingMode, nfc · c2abdec7
  Chen Zheng authored Jul 28, 2020
  
  c2abdec7
- [X86] Detect if EFLAGs is live across XBEGIN pseudo instruction. Add it as... · 647e861e
  Craig Topper authored Jul 27, 2020
  647e861e
- GlobalISel: Don't fail translate on intrinsics with metadata · 5f802be4
  Matt Arsenault authored Jul 21, 2020
  
  5f802be4
- TableGen/GlobalISel: Allow output instructions with multiple defs · ee3feef5
  Matt Arsenault authored Jul 13, 2020
  ee3feef5
- [llvm][CodeGen] Addressing modes for SVE ldN. · adb28e0f
  Francesco Petrogalli authored Jul 06, 2020
  adb28e0f
Jul 27, 2020
- Revert "[PowerPC] Remove QPX/A2Q BGQ/BGP CNK support" · bf544fa1
  Jinsong Ji authored Jul 27, 2020
  bf544fa1
- Rename t2-reduce-size -> thumb2-reduce-size · beb7e3bb
  Arthur Eubanks authored Jul 27, 2020
  beb7e3bb
- [PowerPC] Remove QPX/A2Q BGQ/BGP CNK support · adffce71
  Jinsong Ji authored Jul 27, 2020
  adffce71
- Prefix some AArch64/ARM passes with "aarch64-"/"arm-" · 2a672767
  Arthur Eubanks authored Jul 27, 2020
  2a672767
- [X86][SSE] Relax 128-bit restriction on... · 4d84d949
  Simon Pilgrim authored Jul 27, 2020
  4d84d949
- [XCOFF][AIX] Handle llvm.used and llvm.compiler.used global array · c25f61cf
  jasonliu authored Jul 27, 2020
  c25f61cf
- [AArch64] fjcvtzs,rmif,cfinv,setf* all clobber nzcv · f5e1ec8c
  Jon Roelofs authored Jul 14, 2020
  f5e1ec8c
- [X86][AVX] Fold extract_subvector(truncate(x),0) -> truncate(extract_subvector(x),0) · ab4ffa52
  Simon Pilgrim authored Jul 27, 2020
  ab4ffa52
- [AMDGPU] Make generating cache invalidating instructions optional · 590dd73c
  Piotr Sobczak authored Jul 23, 2020
  590dd73c
- [SVE] Don't use LocalStackAllocation for SVE objects · 14bc85e0
  David Sherwood authored Jul 14, 2020
  14bc85e0
- AMDGPU/GlobalISel: Don't assert in LegalizerInfo constructor · e97aa560
  Matt Arsenault authored Jul 26, 2020
  e97aa560
- [Scheduling] Improve group algorithm for store cluster · a6e9f526
  QingShan Zhang authored Jul 27, 2020
  a6e9f526
Jul 26, 2020
- [X86] Turn X86DAGToDAGISel::tryVPTERNLOG into a fully custom instruction... · df12524e
  Craig Topper authored Jul 26, 2020
  df12524e
- [X86][SSE] lowerV2I64Shuffle - use undef elements in PSHUFD mask widening · 17eafe08
  Simon Pilgrim authored Jul 26, 2020
  17eafe08
- AMDGPU/GlobalISel: Fix not constraining ds_append/consume operands · d35e2c10
  Matt Arsenault authored Jul 25, 2020
  
  d35e2c10
- GlobalISel: Handle G_PTR_ADD in narrowScalar · f6176f8a
  Matt Arsenault authored Jul 25, 2020
  
  f6176f8a
- GlobalISel: Handle fewerElementsVector for G_PTR_ADD · 3e8bb7a0
  Matt Arsenault authored Jul 25, 2020
  
  3e8bb7a0
- AMDGPU/GlobalISel: Make sure <2 x s1> phis are scalarized · bcf5184a
  Matt Arsenault authored Jul 25, 2020
  
  bcf5184a
- AMDGPU/GlobalISel: Legalize GDS atomics · 6f961a1e
  Matt Arsenault authored Jul 25, 2020
  6f961a1e
- AMDGPU/GlobalISel: Pack constant G_BUILD_VECTOR_TRUNCs when selecting · 58191599
  Matt Arsenault authored Jul 18, 2020
  
  58191599
- GlobalISel: Handle 'n' inline asm constraint · 61ced4b8
  Matt Arsenault authored Jul 26, 2020
  
  61ced4b8
- AMDGPU/GlobalISel: Sign extend integer constants · 4033aa14
  Matt Arsenault authored Jul 25, 2020
  4033aa14