Commits · e1e260cc64bd900d5f3f88187c60cb02d3a805f5 · Roger Ferrer / llvm-epi · GitLab

Nov 09, 2022
- [AArch64][SME] Disable GlobalISel/FastISel for SME functions. · e1e260cc
  Sander de Smalen authored Nov 09, 2022
  e1e260cc
- [amdgpu][lds] Use a consistent order of fields in generated structs · e9a2aa63
  Jon Chesterfield authored Nov 09, 2022
  e9a2aa63
- [AArch64] NFC: Remove unused parameter from allocateLazySaveBuffer · a7a0b825
  Sander de Smalen authored Nov 08, 2022
  
  a7a0b825
- [X86] Replace unnecessary CVTSD2SI/CVTSS2SI overrides with better base class defs · a2097449
  Simon Pilgrim authored Nov 09, 2022
  a2097449
- [AArch64][SVE2] Add the SVE2.1 integer quadword reduction instructions · 835de8dc
  David Sherwood authored Nov 03, 2022
  835de8dc
- [AArch64] Add support for the Cortex-X3 CPU · 9d1ff787
  Victor Campos authored Oct 19, 2022
  9d1ff787
- [M68k] Add support for atomic instructions · e086b24d
  Sheng authored Nov 09, 2022
  e086b24d
- [M68k] Replace `IsM680x0` with predicates `AtLeastM680x0` · c7d6a0f6
  Sheng authored Nov 09, 2022
  c7d6a0f6
- [AArch64] Support all extend/shift op for pattern: (ExtendOrShfitNode - Y) + Z... · a3623128
  chenglin.bi authored Nov 09, 2022
  a3623128
- [AArch64][SVE2] Add the SVE2.1 quadword structured load/store instructions · 78f11a39
  David Sherwood authored Nov 07, 2022
  78f11a39
- [X86] Support -march=sierraforest, grandridge, graniterapids. · 84a18a26
  Freddy Ye authored Nov 09, 2022
  84a18a26
- [RISCV] Add support for static chain · f4f6c63f
  melonedo authored Aug 16, 2022
  f4f6c63f
- [X86] Add In64BitMode requirement for MMXRI · b17b25dd
  Haohai Wen authored Nov 09, 2022
  b17b25dd
Nov 08, 2022
- [AArch64]Combine BFXIL to ORR with right shift for ISD::OR instruction selection · e4e7bdeb
  Mingming Liu authored Nov 04, 2022
  e4e7bdeb
- [SVE] Extend getMemVTFromNode to cover the sret variants of sve.ld2/3/4. · df8e0ce5
  Paul Walker authored Aug 22, 2022
  df8e0ce5
- [X86] SkylakeClientModel - fix instregex typo. NFCI. · 1dd06138
  Simon Pilgrim authored Nov 08, 2022
  1dd06138
- [AArch64][SVE2] Add the SVE2.1 pmov instructions · b048b1b7
  David Sherwood authored Nov 07, 2022
  b048b1b7
- [X86] CVTTSS2SI64rm has the same scheduler def as (V)CVTSS2SI64rm · 471f2cff
  Simon Pilgrim authored Nov 08, 2022
  471f2cff
- Reland "[llvm][NFC] Use c++17 style variable type traits" · 6aa050a6
  Nathan James authored Nov 08, 2022
  6aa050a6
- Revert "[llvm][NFC] Use c++17 style variable type traits" · 632a389f
  Nathan James authored Nov 08, 2022
  632a389f
- [AArch64]SME2 Single and Multi vector Shift and Multiply instructions · d917276c
  Caroline Concatto authored Nov 08, 2022
  d917276c
- [llvm][NFC] Use c++17 style variable type traits · 1834a310
  Nathan James authored Nov 08, 2022
  1834a310
- [AMDGPU] Declutter applyPreexistingWaitcnt() · 69dd9910
  Stephen Thomas authored Nov 08, 2022
  69dd9910
- AMDGPU/GlobalISel: Fix combine crash because LI is not set in prelegalizer · 838d5d37
  Petar Avramovic authored Nov 08, 2022
  838d5d37
- [LoongArch] Add support for the BranchRelaxation pass · 57ad3f1d
  Xiaodong Liu authored Nov 02, 2022
  57ad3f1d
- [AArch64][SVE2] Add the SVE2.1 dupq and extq instructions · 8f60eee9
  David Sherwood authored Nov 07, 2022
  8f60eee9
- [AArch64]SME2 MOV Instructions · 1a917568
  Caroline Concatto authored Nov 02, 2022
  1a917568
- [AArch64][SVE2] Add the SVE2.1 FP quadword reduction instructions · 17813095
  David Sherwood authored Nov 03, 2022
  17813095
- [AMDGPU][GlobalISel] Support mad/fma_mix selection · 767999fc
  Pierre van Houtryve authored Sep 28, 2022
  767999fc
- [AMDGPU] Add & use `hasNamedOperand`, NFC · 7425077e
  Pierre van Houtryve authored Nov 07, 2022
  7425077e
- [SIFoldOperands] Small code cleanups, NFC. · b5f99723
  Pierre van Houtryve authored Nov 07, 2022
  b5f99723
- [SIFoldOperands] Move `isFoldableCopy` into a separate helper, NFC. · 70c781f4
  Pierre van Houtryve authored Nov 07, 2022
  70c781f4
- [X86] Add In64BitMode predicates for LOCK_INC64m, LOCK_DEC64m · 1c355352
  Haohai Wen authored Nov 08, 2022
  1c355352
Nov 07, 2022
- AMDGPU: Fix DivergenceAnalysis for llvm.read_register · 583450fa
  Matt Arsenault authored Oct 31, 2022
  583450fa
- [AArch64][SVE2] Add the SVE2.1 quadword variants of ld1w/ld1d/st1w/st1d · a9d7b18b
  David Sherwood authored Nov 01, 2022
  a9d7b18b
- [AArch64][SVE2] Add the SVE2.1 BF16 instructions · cf69895a
  David Sherwood authored Nov 02, 2022
  cf69895a
- [X86] Folded MOVDDUPrm has the same sched behaviour as MOVSHDUPrm/MOVSLDUPrm on Haswell/IceLake · 5c0cb757
  Simon Pilgrim authored Nov 07, 2022
  5c0cb757
- [AArch64] Add SME2.1 target feature for Armv9-A 2022 Architecture Extension · 12a6572d
  David Sherwood authored Nov 03, 2022
  12a6572d
- [AMDGPU][MC][GFX11][NFC] Correct VINTERP src operands · 8f689521
  Dmitry Preobrazhensky authored Nov 07, 2022
  8f689521
- [AMDGPU][MC][GFX10+] Enable literal operands with permlane16/permlanex16 · 6e279f5b
  Dmitry Preobrazhensky authored Nov 07, 2022
  6e279f5b