Commits · e38c5fded6dbff07d3ae961c32be3a3d5dfd045a · Roger Ferrer / llvm-epi · GitLab

Apr 20, 2022
- AArch64/GlobalISel: Remove some null checks for getVRegDef · e38c5fde
  Matt Arsenault authored Apr 09, 2022
  e38c5fde
- AArch64/GlobalISel: Remove asserts on copy instructions · 96c91907
  Matt Arsenault authored Apr 09, 2022
  96c91907
- [DFSan] Print an error before calling null extern_weak functions, incase dfsan... · 204c12ee
  Andrew Browne authored Apr 19, 2022
  204c12ee
- [msan] Destroy ConstantTokenNone before types above · 700442de
  Vitaly Buka authored Apr 19, 2022
  700442de
- [msan] Disable assert with msan · 33c5d8f9
  Vitaly Buka authored Apr 19, 2022
  33c5d8f9
- [SPIR-V](6/6) Add the module analysis pass and the simplest tests · 153dee34
  Ilia Diachkov authored Apr 14, 2022
  153dee34
- [SPIR-V](5/6) Add LegalizerInfo, InstructionSelector and utilities · eab7d363
  Ilia Diachkov authored Apr 14, 2022
  eab7d363
- [SPIR-V](4/6) Add target lowering, TargetMachine and AsmPrinter · ec259036
  Ilia Diachkov authored Apr 14, 2022
  ec259036
- [SPIR-V](3/6) Add MC layer, object file support, and InstPrinter · 6c69427e
  Ilia Diachkov authored Apr 14, 2022
  6c69427e
- [SPIR-V](2/6) Add SPIRV target description files · 40114dd5
  Ilia Diachkov authored Apr 14, 2022
  40114dd5
- [SPIR-V](1/6) Add stub for SPIRV backend · 7fd4622d
  Ilia Diachkov authored Apr 14, 2022
  7fd4622d
- AMDGPU: More mad_64_32 test cases for multiple uses · b39d34de
  Nicolai Hähnle authored Apr 19, 2022
  b39d34de
- [BPF] Fix a bug in BPFMISimplifyPatchable pass · 497a5f04
  Peter Klausler authored Apr 04, 2022
  497a5f04
- [RISCV] Fold (xor (sllw 1, x), -1) -> (rolw ~1, x). · 6db0afb4
  Craig Topper authored Apr 19, 2022
  6db0afb4
Apr 19, 2022
- [BPF] Emit fatal error if out of range for FK_PCRel_2 branch target · 954ba604
  Yonghong Song authored Apr 15, 2022
  954ba604
- [gn build] Port bac6cd5b · 858e40d8
  LLVM GN Syncbot authored Apr 19, 2022
  
  858e40d8
- [misexpect] Re-implement MisExpect Diagnostics · bac6cd5b
  Paul Kirth authored Apr 01, 2022
  bac6cd5b
- [gn build] Port c57f0341 · b5e962a5
  LLVM GN Syncbot authored Apr 19, 2022
  
  b5e962a5
- [BuildLibCalls] Introduce getOrInsertLibFunc() for use when building libcalls. · 0f8c6267
  Jonas Paulsson authored Apr 14, 2022
  0f8c6267
- [InstCombine] C0 shift (X add nuw C) --> (C0 shift C) shift X · 8a9c70fc
  Sanjay Patel authored Apr 19, 2022
  8a9c70fc
- [InstCombine] add tests for shift-of-add with constants; NFC · a9aa14e0
  Sanjay Patel authored Apr 19, 2022
  
  a9aa14e0
- [NFC][SLP] Improved description of getShallowScore() and getScoreAtLevelRec() · 8d4b5e08
  Vasileios Porpodas authored Apr 19, 2022
  8d4b5e08
- [IRSim] Ignore debug instructions when creating canonical numbering · 3de29ad2
  Andrew Litteken authored Apr 16, 2022
  3de29ad2
- [Go] Remove PopulateLTOPassManager binding after D123882 · 06cafd04
  Fangrui Song authored Apr 19, 2022
  
  06cafd04
- [InstCombine] add tests for freeze of partial undef vector constants; NFC · 5f7c3854
  Sanjay Patel authored Apr 18, 2022
  
  5f7c3854
- [OCaml] Fix pass builder test · f2d955a8
  Nikita Popov authored Apr 19, 2022
  f2d955a8
- [Test] Add more tests showing duplicate PHIs generated by RS4GC (NFC) · 084ad1eb
  Dmitry Makogon authored Apr 19, 2022
  084ad1eb
- [PerfectShuffle] Remove unused variables from D123386. NFC · cc034141
  David Green authored Apr 19, 2022
  
  cc034141
- [VPlan] Remove unused SCEV forward declaration (NFC). · 4026b718
  Florian Hahn authored Apr 19, 2022
  
  4026b718
- [SystemZ] Handle SystemZ specific inline assembly address operands. · 4aa5dc15
  Jonas Paulsson authored Mar 22, 2022
  4aa5dc15
- [llvm-ar][test] Rename two tests and use correct thin command · 42865819
  gbreynoo authored Apr 19, 2022
  42865819
- [AArch64] Add lane moves to PerfectShuffle tables · 73dc9964
  David Green authored Apr 19, 2022
  73dc9964
- [SLP][NFC]Add a test for reducing same values, NFC. · 7adfa31b
  Alexey Bataev authored Apr 19, 2022
  
  7adfa31b
- Revert "[SLP]Improve reductions analysis and emission, part 1." · 88357192
  Alexey Bataev authored Apr 19, 2022
  88357192
- [AArch64] Only mark cost 1 perfect shuffles as legal · cc9495f6
  David Green authored Apr 19, 2022
  cc9495f6
- [VPlan] Expand induction step in VPlan pre-header. · a65f2730
  Florian Hahn authored Apr 19, 2022
  a65f2730
- [AArch64] Cost all perfect shuffles entries as cost 1 · 50af8270
  David Green authored Apr 19, 2022
  50af8270
- Fix SLP score for out of order contiguous loads · 8daffd1d
  Alban Bridonneau authored Apr 19, 2022
  8daffd1d
- [AMDGPU][MC] Corrected error message "image data size does not match dmask and tfe" · e01dbabd
  Dmitry Preobrazhensky authored Apr 19, 2022
  e01dbabd
- [AMDGPU] Select d16 stores even when sramecc is enabled · f707e125
  Jay Foad authored Jun 22, 2021
  f707e125