Commits · e3fa2b1eab60342dc882b7b888658b03c472fa2b · Roger Ferrer / llvm-epi · GitLab

Jul 16, 2021
- Revert "[RISCV] Lower more BUILD_VECTOR sequences to RVV's VID" · e3fa2b1e
  Fraser Cormack authored Jul 16, 2021
  e3fa2b1e
- [RISCV] Lower more BUILD_VECTOR sequences to RVV's VID · a6ca88e9
  Fraser Cormack authored Jun 24, 2021
  a6ca88e9
Jul 14, 2021
- [RISCV] Fix the neutral element in vector 'fadd' reductions · 03a4702c
  Fraser Cormack authored Jul 13, 2021
  03a4702c
Jul 13, 2021
- [RISCV] Pass undef VECTOR_SHUFFLE indices on to BUILD_VECTOR · d991b721
  Fraser Cormack authored Jun 23, 2021
  d991b721
Jul 12, 2021
- [SelectionDAG][RISCV] Support @llvm.vscale.i64() on 32-bit targets. · ec1cdee6
  Eli Friedman authored Jul 12, 2021
  ec1cdee6
Jul 06, 2021
- [RISCV] Add support for matching vwmul(u) and vwmacc(u) from fixed vectors. · 2b5e5311
  Craig Topper authored Jul 06, 2021
  2b5e5311
Jun 30, 2021
- CodeGen: Print/parse LLTs in MachineMemOperands · fae05692
  Matt Arsenault authored May 19, 2021
  fae05692
Jun 27, 2021
- Revert "[RISCV] Use zexti32/sexti32 in srliw/sraiw isel patterns to improve... · 010f0f00
  Craig Topper authored Jun 27, 2021
  010f0f00
Jun 26, 2021
- [RISCV] Use zexti32/sexti32 in srliw/sraiw isel patterns to improve usage of those instructions. · 81b2f959
  Craig Topper authored Jun 26, 2021
  
  81b2f959
Jun 25, 2021
- [RISCV] Permit larger RVV stacks and stack offsets · ab1bd255
  Fraser Cormack authored Jun 22, 2021
  ab1bd255
Jun 24, 2021
- [RISCV] Lower RVV vector SELECTs to VSELECTs · a4729f7f
  Fraser Cormack authored Jun 23, 2021
  a4729f7f
Jun 23, 2021
- [Verifier] Fail on overrunning and invalid indices for {insert,extract} vector intrinsics · 3c4dbf6e
  Joe Ellis authored Jun 18, 2021
  3c4dbf6e
Jun 21, 2021
- [RISCV] Add isel patterns to match vmacc/vmadd/vnmsub/vnmsac from add/sub and mul. · 9080659a
  Craig Topper authored Jun 21, 2021
  9080659a
Jun 18, 2021
- [RISCV] Teach vsetvli insertion to remember when predecessors have same AVL... · ac87133f
  Craig Topper authored Jun 18, 2021
  ac87133f
Jun 17, 2021
- [RISCV][VP] Lower FP VP ISD nodes to RVV instructions · fed1503e
  Fraser Cormack authored Jun 14, 2021
  fed1503e
Jun 14, 2021
- [RISCV] Transform unaligned RVV vector loads/stores to aligned ones · c75e454c
  Fraser Cormack authored Jun 09, 2021
  c75e454c
Jun 11, 2021
- [RISCV] Avoid scalar outgoing argumetns overwriting vector frame objects. · 643b6407
  Hsiangkai Wang authored Jun 03, 2021
  643b6407
Jun 09, 2021
- [ValueTypes][RISCV] Cap RVV fixed-length vectors by size · 502edebd
  Fraser Cormack authored Jun 07, 2021
  502edebd
- [RISCV] Support CONCAT_VECTORS on scalable masks · e8f1f891
  Fraser Cormack authored Jun 08, 2021
  e8f1f891
- [RISCV][NFC] Add a single space after comma for VType · 242ddd50
  Jim Lin authored Jun 08, 2021
  242ddd50
Jun 08, 2021
- [RISCV] Remove dead code from fixed-vectors-abs.ll test cases. NFC · c09b3755
  Craig Topper authored Jun 08, 2021
  c09b3755
- Further improve register allocation for vwadd(u).wv, vwsub(u).wv, vfwadd.wv, and vfwsub.wv. · 8b4c80d3
  Craig Topper authored Jun 08, 2021
  8b4c80d3
- [RISCV] Remove ForceTailAgnostic flag from vmv.s.x, vfmv.s.f and reductions. · c57bce9c
  Craig Topper authored Jun 08, 2021
  c57bce9c
- [RISCV] Add a test case showing inefficient vector codegen · ccd1e087
  Fraser Cormack authored Jun 08, 2021
  
  ccd1e087
- [DAG] Allow isNullOrNullSplat to see truncated zeroes · b889c6ee
  David Green authored Jun 08, 2021
  b889c6ee
- [RISCV] Use 0 for Log2SEW for vle1/vse1 intrinsics to enable vsetvli optimization. · 7c4e9a68
  Craig Topper authored Jun 07, 2021
  7c4e9a68
- [RISCV] Masked compares should use a tail agnostic policy. · ae3ab4f0
  Craig Topper authored Jun 07, 2021
  ae3ab4f0
Jun 04, 2021
- [RISCV] Teach vsetvli insertion pass that operations on masks don't care about SEW/LMUL. · c653711f
  Craig Topper authored Jun 04, 2021
  c653711f
- [SelectionDAG] Extend FoldConstantVectorArithmetic to SPLAT_VECTOR · aec9cbbe
  Fraser Cormack authored May 27, 2021
  aec9cbbe
Jun 03, 2021
- [RISCV] Precommit a test case to show overwriting vector frame objects. · 9d4922ea
  Hsiangkai Wang authored Jun 03, 2021
  
  9d4922ea
- [RISCV] Reserve an emergency spill slot for any RVV spills · 8790e852
  Fraser Cormack authored May 26, 2021
  8790e852
- [CodeGen] Fix a scalable-vector crash in VSELECT legalization · 1de1887f
  Fraser Cormack authored Jun 02, 2021
  1de1887f
- [ValueTypes] Fix scalable-vector changeExtendedVectorTypeToInteger · 2dd20a31
  Fraser Cormack authored Jun 02, 2021
  2dd20a31
Jun 02, 2021
- [RISCV][NFC] Add '+mattr=+experimental-v' to RVV test · 1cea1189
  Fraser Cormack authored Jun 02, 2021
  
  1cea1189
- [RISCV] Expand unaligned fixed-length vector memory accesses · 3b0a33d0
  Fraser Cormack authored May 14, 2021
  3b0a33d0
- [RISCV] Improve register allocation for masked vwadd(u).wv, vwsub(u).wv, vfwadd.wv, and vfwsub.wv. · 41ff1e0e
  Craig Topper authored Jun 01, 2021
  41ff1e0e
Jun 01, 2021
- [RISCV] Remove earlyclobber from vnsrl/vnsra/vnclip(u) when the source and... · 896f9bc3
  Craig Topper authored Jun 01, 2021
  896f9bc3
- [RISCV] Remove earlyclobber from compares with LMUL<=1. · 5a5219a0
  Craig Topper authored Jun 01, 2021
  5a5219a0
- [RISCV] Support vector types in combination with fastcc · 4f500c40
  Fraser Cormack authored May 13, 2021
  4f500c40
May 31, 2021
- [RISCV] Scale scalably-typed split argument offsets by VSCALE · 2b37c405
  Fraser Cormack authored May 27, 2021
  2b37c405