Commits · e415cb1d61e798b6d69b5960a90f00518ca5008f · Roger Ferrer / llvm-epi · GitLab

Oct 31, 2022
- [LoongArch] Support inline asm operand modifier 'z' · e415cb1d
  Weining Lu authored Oct 31, 2022
  e415cb1d
- [LoongArch] Replace assertion by error message while lowering RETURNADDR and FRAMEADDR · be8a2b98
  gonglingqin authored Oct 31, 2022
  be8a2b98
- [Clang][LoongArch] Support inline asm constraint 'J' · cd0174aa
  Weining Lu authored Oct 31, 2022
  cd0174aa
- [NFC][m68k] Add pipeline.ll · dbfa4a0a
  Sheng authored Oct 31, 2022
  
  dbfa4a0a
Oct 30, 2022
- [llvm-objdump] Add --no-print-imm-hex to tests depending on it. · 75cdab6d
  Daniel Thornburgh authored Oct 28, 2022
  75cdab6d
- [test] Remove readonly from some parameters that are written through in tests. · f3d49dbc
  Patrick Walton authored Oct 27, 2022
  f3d49dbc
Oct 29, 2022
- [Hexagon] Break up vectors into HVX-sized chunks in HvxIdioms · 9422a8d9
  Krzysztof Parzyszek authored Oct 25, 2022
  9422a8d9
- Recommit [AArch64] Optimize memcmp when the result is tested for [in]equality with 0 · 63a46385
  zhongyunde authored Oct 30, 2022
  63a46385
- [ARC] Regenerate ldst.ll · adf3daae
  Simon Pilgrim authored Oct 29, 2022
  adf3daae
- [DAG] Enable combineShiftOfShiftedLogic folds after type legalization · 78739fdb
  Simon Pilgrim authored Oct 29, 2022
  78739fdb
- ARM: Fix stack warning test · a8762195
  Matt Arsenault authored Oct 28, 2022
  
  a8762195
- DiagnosticInfo: Report function location for resource limits · c62745e1
  Matt Arsenault authored Oct 27, 2022
  c62745e1
- Revert "[AArch64] Optimize memcmp when the result is tested for [in]equality with 0" · 1c068175
  Paul Kirth authored Oct 28, 2022
  1c068175
Oct 28, 2022
- [RISCV] Optimize i64 insertelt on RV32. · 6a794419
  Craig Topper authored Oct 28, 2022
  6a794419
- [DAG] ExpandIntRes_MINMAX - simplify cases with sufficient number of sign bits · 69d117ed
  Simon Pilgrim authored Oct 28, 2022
  69d117ed
- [X86] Add basic test coverage for Issue #58630 · 7c44b484
  Simon Pilgrim authored Oct 28, 2022
  7c44b484
- [RISCV] Adjust RV64I data layout by using n32:64 in layout string · 974e2e69
  Craig Topper authored Oct 28, 2022
  974e2e69
- Revert "[MachineCSE] Allow PRE of instructions that read physical registers" · 7a7b36e9
  John Brawn authored Oct 28, 2022
  7a7b36e9
- [SDAG] avoid crash from mismatched types in scalar-to-vector fold · 1e7c1dd6
  Sanjay Patel authored Oct 28, 2022
  1e7c1dd6
- [DAG] visitXOR - fold XOR(A,B) -> OR(A,B) iff A and B have no common bits · d47f056c
  Simon Pilgrim authored Oct 28, 2022
  d47f056c
- [AMDGPU] Regenerate checks in waitcnt-overflow.mir. NFC. · dc398199
  Jay Foad authored Oct 28, 2022
  
  dc398199
- [LoongArch] Add emergency spill slot for GPR for large frames · 4e2364a2
  wanglei authored Oct 28, 2022
  4e2364a2
- [LoongArch] Split SP adjustment · f589e506
  wanglei authored Oct 28, 2022
  f589e506
- Revert "[AArch64] Adjust operand sequence for Add+Sub to combine more inline shift" · dfb16bd5
  chenglin.bi authored Oct 28, 2022
  dfb16bd5
- [ARM] Use DefaultAttrsIntrinsics · 9481e4ba
  Nikita Popov authored Oct 26, 2022
  9481e4ba
- [AArch64][SME] Set fn attributes correctly on __arm_tpidr2_save call. · e82cace1
  Sander de Smalen authored Oct 28, 2022
  e82cace1
- [DAGCombiner] Use `getAnyExtOrTrunc` instead of TRUNCATE in ExtractVectorElt combine · 088a8168
  Pierre van Houtryve authored Oct 28, 2022
  088a8168
- [X86] Add AVX-VNNI-INT8 instructions. · 23f02693
  Freddy Ye authored Oct 28, 2022
  23f02693
- [X86] Add AVX-IFMA instructions. · 0e720e6a
  Freddy Ye authored Oct 28, 2022
  0e720e6a
- [AMDGPU] Add pseudo wavemode to optimize strict_wqm · a3646ec1
  Carl Ritson authored Oct 28, 2022
  a3646ec1
- [AArch64] Optimize memcmp when the result is tested for [in]equality with 0 · 01ff5115
  zhongyunde authored Oct 28, 2022
  01ff5115
Oct 27, 2022
- [AArch64][SVE2] Add the SVE2.1 pext and ptrue predicate-as-counter instructions · 891aaff9
  David Sherwood authored Oct 25, 2022
  891aaff9
- [RISCV] Fix an obvious CSE opportunity in LSR test case. NFC · 8fa32a74
  Craig Topper authored Oct 27, 2022
  
  8fa32a74
- [LegalizeVectorOps][X86][RISCV] Expand vector S/USHLSAT instead of unrolling. · 00d93def
  Craig Topper authored Oct 27, 2022
  00d93def
- [LoongArch] Add codegen support for cmpxchg on LA64 · bba97c3c
  gonglingqin authored Oct 27, 2022
  bba97c3c
- [MachineCSE] Allow PRE of instructions that read physical registers · 628467e5
  John Brawn authored Oct 27, 2022
  628467e5
- [X86][1/2] SUPPORT RAO-INT · b51b90d6
  Phoebe Wang authored Oct 27, 2022
  b51b90d6
- [AArch64] Adjust operand sequence for Add+Sub to combine more inline shift · ada9ab61
  chenglin.bi authored Oct 27, 2022
  ada9ab61
- [CodeGen] Improve large stack frame diagnostic · 2e1e2f52
  Paul Kirth authored Oct 21, 2022
  2e1e2f52
Oct 26, 2022
- [RISCV] Inline scalar ceil/floor/trunc/rint/round/roundeven. · e94dc58d
  Craig Topper authored Oct 26, 2022
  e94dc58d