- Nov 24, 2016
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Abhilash Bhandari authored
llvm-svn: 287891
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Simon Pilgrim authored
llvm-svn: 287889
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Benjamin Kramer authored
No functional change. llvm-svn: 287888
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Simon Pilgrim authored
Vectorize UINT_TO_FP v2i32 -> v2f64 instead of scalarization (albeit still on the SIMD unit). The codegen matches that generated by legalization (and is in fact used by AVX for UINT_TO_FP v4i32 -> v4f64), but has to be done in the x86 backend to account for legalization via 4i32. Differential Revision: https://reviews.llvm.org/D26938 llvm-svn: 287886
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Simon Pilgrim authored
Use 512-bit instructions with subvector insertion/extraction like we do in a number of similar circumstances llvm-svn: 287882
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Simon Pilgrim authored
[X86][AVX512DQVL] Add awareness of vcvtqq2ps and vcvtuqq2ps implicit zeroing of upper 64-bits of xmm result llvm-svn: 287878
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Simon Pilgrim authored
llvm-svn: 287877
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Simon Pilgrim authored
llvm-svn: 287876
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Nikolai Bozhenov authored
The bug arises during register allocation on i686 for CMPXCHG8B instruction when base pointer is needed. CMPXCHG8B needs 4 implicit registers (EAX, EBX, ECX, EDX) and a memory address, plus ESI is reserved as the base pointer. With such constraints the only way register allocator would do its job successfully is when the addressing mode of the instruction requires only one register. If that is not the case - we are emitting additional LEA instruction to compute the address. It fixes PR28755. Patch by Alexander Ivchenko <alexander.ivchenko@intel.com> Differential Revision: https://reviews.llvm.org/D25088 llvm-svn: 287875
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Nikolai Bozhenov authored
Move the definitions of three variables out of the switch. Patch by Alexander Ivchenko <alexander.ivchenko@intel.com> Differential Revision: https://reviews.llvm.org/D25192 llvm-svn: 287874
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Nikolai Bozhenov authored
- It does not modify the input instruction - Second operand of any address is always an Index Register, make sure we actually check for that, instead of a check for an immediate value Patch by Alexander Ivchenko <alexander.ivchenko@intel.com> Differential Revision: https://reviews.llvm.org/D24938 llvm-svn: 287873
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Dylan McKay authored
llvm-svn: 287871
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Simon Pilgrim authored
Replace the CVTTPD2DQ/CVTTPD2UDQ and CVTDQ2PD/CVTUDQ2PD opcodes with general versions. This is an initial step towards similar FP_TO_SINT/FP_TO_UINT and SINT_TO_FP/UINT_TO_FP lowering to AVX512 CVTTPS2QQ/CVTTPS2UQQ and CVTQQ2PS/CVTUQQ2PS with illegal types. Differential Revision: https://reviews.llvm.org/D27072 llvm-svn: 287870
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Malcolm Parsons authored
Summary: The default constructor for a StringRef stores an empty string. Reviewers: beanz, zturner Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D27067 llvm-svn: 287857
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Jacob Baungard Hansen authored
Patch by Daniel Cederman. Reviewers: stoklund, arsenm Subscribers: arsenm, llvm-commits Differential Revision: https://reviews.llvm.org/D27046 llvm-svn: 287856
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Craig Topper authored
llvm-svn: 287854
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Craig Topper authored
llvm-svn: 287853
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Peter Collingbourne authored
This lets us remove a use of IRObjectFile::getModule() in llvm-nm. Differential Revision: https://reviews.llvm.org/D27074 llvm-svn: 287846
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Peter Collingbourne authored
Change the IRObjectFile symbol iterator to be a pointer into a vector of PointerUnions representing either IR symbols or asm symbols. This change is in preparation for a future change for supporting multiple modules in an IRObjectFile. Although it causes an increase in memory consumption, we can deal with that issue separately by introducing a bitcode symbol table. Differential Revision: https://reviews.llvm.org/D26928 llvm-svn: 287845
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Matt Arsenault authored
llvm-svn: 287844
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Matt Arsenault authored
The scavenger was not passed if requiresFrameIndexScavenging was enabled. I need to be able to test for the availability of an unallocatable register here, so I can't create a virtual register for it. It might be better to just always use the scavenger and stop creating virtual registers. llvm-svn: 287843
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Matt Arsenault authored
Since m0 isn't allocatable it should never be spilled anymore. llvm-svn: 287842
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Matt Arsenault authored
m0 may need to be written for spill code, so we don't want general code uses relying on the value stored in it. This introduces a few code quality regressions where copies from m0 are not coalesced into copies of a copy of m0. llvm-svn: 287841
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Davide Italiano authored
llvm-svn: 287840
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Greg Clayton authored
This patch makes AsmPrinter less reliant on DwarfDebug by relying on the DWARF version in the AsmPrinter's MCStreamer's MCContext. This allows us to remove the redundant DWARF version from DwarfDebug. It also lets us change code that used to access the AsmPrinter's DwarfDebug just to get to the DWARF version by changing the DWARF version accessor on AsmPrinter so that it grabs the version from its MCStreamer's MCContext. Differential Revision: https://reviews.llvm.org/D27032 llvm-svn: 287839
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Eugene Zelenko authored
[DebugInfo] Fix some Clang-tidy modernize-use-default and Include What You Use warnings; other minor fixes (NFC). Per Zachary Turner and Mehdi Amini suggestion to make only post-commit reviews. llvm-svn: 287838
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- Nov 23, 2016
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Simon Pilgrim authored
[X86][SSE] Add awareness of (v)cvtpd2dq and vcvtpd2udq implicit zeroing of upper 64-bits of xmm result We've already added the equivalent for (v)cvttpd2dq (rL284459) and vcvttpd2udq llvm-svn: 287835
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Eugene Zelenko authored
[IR] Fix some Clang-tidy modernize-use-default, modernize-use-equal-delete and Include What You Use warnings; other minor fixes (NFC). Per Zachary Turner and Mehdi Amini suggestion to make only post-commit reviews. llvm-svn: 287834
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Nicolai Haehnle authored
Summary: Reduce indentation level; preparation for D24956. Reviewers: efriedma Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D27063 llvm-svn: 287831
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Simon Pilgrim authored
llvm-svn: 287821
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Matt Arsenault authored
Move code down to use, reorder to avoid hard to follow immediate folding logic. llvm-svn: 287818
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Matt Arsenault authored
The uint8_t was printed as a char which didn't really work. llvm-svn: 287817
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Simon Pilgrim authored
llvm-svn: 287813
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Matt Arsenault authored
llvm-svn: 287808
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Matt Arsenault authored
In the scalar case, there's no reason to add an additional def of the same register. llvm-svn: 287807
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Matt Arsenault authored
The size and offset were wrong. The size of the object was being used for the size of the access, when here it is really being split into 4-byte accesses. The underlying object size is set in the MachinePointerInfo, which also didn't have the offset set. llvm-svn: 287806
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Vedant Kumar authored
This reverts commit r287403. It breaks an internal asan bot. According to Kuba, a fix is up for review here: https://reviews.llvm.org/D26929 llvm-svn: 287804
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Meador Inge authored
This patch fixes a small bug where symbols defined in the INIT and FINI sections were incorrectly getting a type of 'n'. Differential Revision: https://reviews.llvm.org/D26937 llvm-svn: 287803
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Meador Inge authored
Undefined and weak symbols don't have a meaningful size or value. As such, nothing should be printed for those attributes (this is already done for the address with 'U') with the BSD format. This matches what GNU nm does. Note that for the POSIX.2 format [1] zero values are still printed for the size and value. This seems in spirit with the format strings in that specification, but is debatable. [1] http://pubs.opengroup.org/onlinepubs/9699919799/ Differential Revision: https://reviews.llvm.org/D26936 llvm-svn: 287802
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Alexey Bataev authored
llvm-svn: 287801
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