Commits · e71e653a5f73dc1597e68b891f26a2db7ffb191a · Roger Ferrer / llvm-epi · GitLab

Jul 31, 2015
- x86: check hasOpaqueSPAdjustment in canRealignStack · e71e653a
  JF Bastien authored Jul 31, 2015
  e71e653a
- WebAssembly: handle unused function arguments. · d7fcc6f9
  JF Bastien authored Jul 31, 2015
  d7fcc6f9
- WebAssembly: print basic integer assembly. · 600aee98
  JF Bastien authored Jul 31, 2015
  600aee98
- [x86] reassociate integer multiplies using machine combiner pass · 9ff46260
  Sanjay Patel authored Jul 31, 2015
  9ff46260
- [AArch64] Favor extended reg patterns for sub · 8a7ef3b2
  Geoff Berry authored Jul 31, 2015
  8a7ef3b2
- Refactor: Simplify boolean conditional return statements in lib/Target/NVPTX · 4be014ae
  Jingyue Wu authored Jul 31, 2015
  4be014ae
- AMDGPU: Fix v16i32 to v16i8 truncstore · e1ce344b
  Matt Arsenault authored Jul 31, 2015
  e1ce344b
- AMDGPU/SI: Set DwarfRegNum · ba013379
  Matt Arsenault authored Jul 31, 2015
  ba013379
- AMDGPU/SI: Remove unused pattern for f32 constant loads · 82325598
  Tom Stellard authored Jul 31, 2015
  82325598
- [ARM] Lower modulo operation to generate __aeabi_divmod on Android · 532a1369
  Sumanth Gundapaneni authored Jul 31, 2015
  532a1369
Jul 30, 2015
- fix memcpy/memset/memmove lowering when optimizing for size · 1166f2ff
  Sanjay Patel authored Jul 30, 2015
  1166f2ff
- AMDGPU: Set SubRegIndex size and offset · 7a0c3a92
  Matt Arsenault authored Jul 30, 2015
  7a0c3a92
- AMDGPU: Fix unreachable when emitting binary debug info · b39e8583
  Matt Arsenault authored Jul 30, 2015
  b39e8583
- AMDGPU/SI: Simplify moveSMRDToVALU() · 4229aa94
  Tom Stellard authored Jul 30, 2015
  4229aa94
- AMDGPU/SI: Remove isTriviallyReMaterializable() function from SIInstrInfo · 9d740760
  Tom Stellard authored Jul 30, 2015
  9d740760
- [mips][FastISel] Remove hidden mips-fast-isel option. · 2041b1dd
  Vasileios Kalintiris authored Jul 30, 2015
  2041b1dd
- [mips][FastISel] Apply only zero-extension to constants prior to their materialization. · 77fb0a3d
  Vasileios Kalintiris authored Jul 30, 2015
  77fb0a3d
- [X86] Recognize "flags" as an identifier, not a register in Intel-syntax inline asm · cdb076b8
  Michael Kuperstein authored Jul 30, 2015
  cdb076b8
- push fast-math check for machine-combiner reassociations into instruction-type check; NFC · 5bfbb36a
  Sanjay Patel authored Jul 30, 2015
  5bfbb36a
- Fix typo "fuction" noticed in comments in AssumptionCache.h, and also all the... · c3890d29
  Nick Lewycky authored Jul 29, 2015
  c3890d29
- Rename hasCompatibleFunctionAttributes->areInlineCompatible based · d566fb12
  Eric Christopher authored Jul 29, 2015
  d566fb12
Jul 29, 2015
- [X86][SSE] Keep 32-bit target i64 vector shifts on SSE unit. · ba10f767
  Simon Pilgrim authored Jul 29, 2015
  ba10f767
- AArch64: use 32-bit MOV rather than UBFX to truncate registers. · 2a9d801f
  Tim Northover authored Jul 29, 2015
  2a9d801f
- [X86][SSE] Vectorize i64 ASHR operations · 86478c69
  Simon Pilgrim authored Jul 29, 2015
  86478c69
- Roll forward r242871 · 3a04dc6e
  Jingyue Wu authored Jul 29, 2015
  3a04dc6e
- Revert "[PeepholeOptimizer] Look through PHIs to find additional register sources" · 38c02506
  Bruno Cardoso Lopes authored Jul 29, 2015
  38c02506
- AArch64: use AddressingModes.h accessors for compare shifts · cf739b8c
  Tim Northover authored Jul 29, 2015
  cf739b8c
- Temporarily revert r242871 · 7ec38530
  Jingyue Wu authored Jul 29, 2015
  7ec38530
- [PPC] Fix PR24216: Don't generate splat for misaligned shuffle mask · 42ddd711
  Bill Schmidt authored Jul 29, 2015
  42ddd711
- [AArch64] Define subtarget feature strict-align. · f53b0403
  Akira Hatanaka authored Jul 29, 2015
  f53b0403
- Fix broken ArrayRef conversion from r243497. · d8a1e542
  Alex Lorenz authored Jul 28, 2015
  d8a1e542
- fix TLI's combineRepeatedFPDivisors interface to return the minimum user threshold · 1dd15598
  Sanjay Patel authored Jul 28, 2015
  1dd15598
- MIR Serialization: Serialize the target index machine operands. · ef5c196f
  Alex Lorenz authored Jul 28, 2015
  ef5c196f
- [ARM] Define subtarget feature strict-align. · 2670f4a5
  Akira Hatanaka authored Jul 28, 2015
  2670f4a5
- AArch64: be careful of large immediates when optimising cmps. · 17ae83a2
  Tim Northover authored Jul 28, 2015
  17ae83a2
Jul 28, 2015
- [PeepholeOptimizer] Look through PHIs to find additional register sources · 3c235763
  Bruno Cardoso Lopes authored Jul 28, 2015
  3c235763
- [mips][FastISel] Fix call lowering by bailing out on "fastcc" calls. · 9876946a
  Vasileios Kalintiris authored Jul 28, 2015
  9876946a
- [mips][FastISel] Fix generated code for IR's select instruction. · 9ec61148
  Vasileios Kalintiris authored Jul 28, 2015
  9ec61148
- AMDGPU: Don't try to use LDS/vector for private if pointer value stored · 7227cc1a
  Matt Arsenault authored Jul 28, 2015
  7227cc1a
- AMDGPU: Fix crash if called function is a bitcast · fdcd39a8
  Matt Arsenault authored Jul 28, 2015
  fdcd39a8