Commits · e7a306310b0bfbd97cdce8f77686b6453fc76bca · Roger Ferrer / llvm-epi · GitLab

Dec 30, 2022
- [AMDGPU][GFX11] Correct tied src2 of v_fmac_f16_e64 · e7a30631
  Dmitry Preobrazhensky authored Dec 30, 2022
  e7a30631
- [AMDGPU][MC][GFX11] Correct encoding of neg modifier for v_dot2_f32_bf16 · 9f40d9ff
  Dmitry Preobrazhensky authored Dec 30, 2022
  9f40d9ff
- [ScheduleDAG] Support REQ_SEQUENCE unscheduling · 98265db8
  Filipp Zhinkin authored Dec 27, 2022
  98265db8
- [RISCV] Use SUB instead of XOR in lowerShiftLeftParts/lowerShiftRightParts./ · a63b7247
  Craig Topper authored Dec 29, 2022
  a63b7247
- [RISCV] RISCVDAGToDAGISel::selectShiftMask to shift by (sub size-1, X). · 7cd72585
  Craig Topper authored Dec 29, 2022
  7cd72585
- AMDGPU/clang: Remove target features from address space test builtins · e630d9b2
  Matt Arsenault authored Nov 28, 2022
  e630d9b2
- DAG: Prevent store value forwarding to distinct addrspace load · 0ec51a46
  Dmitry Borisenkov authored Dec 29, 2022
  0ec51a46
- [RISCV] Teach RISCVDAGToDAGISel::selectShiftMask to bypass adds with constant. · e50976e5
  Craig Topper authored Dec 29, 2022
  e50976e5
Dec 29, 2022
- [NFC][Codegen][X86] zero_extend_vector_inreg.ll: add SSE4.2 runline · c823517e
  Roman Lebedev authored Dec 30, 2022
  
  c823517e
- [DAGCombiner] Try to partition ISD::EXTRACT_VECTOR_ELT to accomodate it's ISD::BUILD_VECTOR users · 248567a3
  Roman Lebedev authored Dec 29, 2022
  248567a3
- [TargetLowering] Teach BuildUDIV to take advantage of leading zeros in the dividend. · 8abd7008
  Craig Topper authored Dec 29, 2022
  8abd7008
- [InstCombine] avoid miscompile in sinkNotIntoLogicalOp() · 30af2e31
  Sanjay Patel authored Dec 29, 2022
  30af2e31
- [InstCombine] add test for miscompile from sinkNotIntoLogicalOp(); NFC · e5a73098
  Sanjay Patel authored Dec 29, 2022
  e5a73098
- [BPF] Use SectionForGlobal() for section names computation in BTF · ed068386
  Eduard Zingerman authored Dec 29, 2022
  ed068386
- [InstSimplify] fold exact divide to poison if it is known to not divide evenly · f0faea57
  Sanjay Patel authored Dec 29, 2022
  f0faea57
- [RISCV] Add fmin/fmax scalar instructions to isAssociativeAndCommutative · af5dd270
  Hsiangkai Wang authored Dec 23, 2022
  af5dd270
- [RISCV] Add integer scalar instructions to isAssociativeAndCommutative · 002005e6
  Hsiangkai Wang authored Dec 22, 2022
  002005e6
- [InstCombine] Fold (X << Z) / (X * Y) -> (1 << Z) / Y · 1f84e72b
  Chenbing Zheng authored Dec 29, 2022
  1f84e72b
- [RISCV] Add Svpbmt extension support. · bd9c0f08
  Yeting Kuo authored Dec 27, 2022
  bd9c0f08
- [RISCV] Add SH1ADD/SH2ADD/SH3ADD to RISCVDAGToDAGISel::hasAllNBitUsers. · 0e9855c1
  Craig Topper authored Dec 28, 2022
  
  0e9855c1
- [RISCV] Prefer ADDI over ORI if the known bits are disjoint. · 79d6e9c7
  Craig Topper authored Dec 28, 2022
  79d6e9c7
- [DFSan] Add `zeroext` attribute for callbacks with 8bit shadow variable arguments · 14ce567f
  Weining Lu authored Dec 29, 2022
  14ce567f
- [NFC][Codegen][X86] Add exhaustive-ish test coverage for ZERO_EXTEND_VECTOR_INREG · 778a7df5
  Roman Lebedev authored Dec 29, 2022
  778a7df5
- [RISCV] Fix mistakes in fixed-vectors-vreductions-mask.ll command lines. NFC · 9b59207a
  Craig Topper authored Dec 28, 2022
  9b59207a
- [RISCV] Add RISCV::XORI to RISCVDAGToDAGISel::hasAllNBitUsers. · 6357b637
  Craig Topper authored Dec 28, 2022
  
  6357b637
Dec 28, 2022
- [RISCV] Support SRLI in hasAllNBitUsers. · cdf09ce7
  Craig Topper authored Dec 28, 2022
  cdf09ce7
- [XRay] Fix Hexagon sled version · 27751bed
  Fangrui Song authored Dec 28, 2022
  27751bed
- [X86] Emit RIP-relative access to local function in PIC medium code model · 82be8a1d
  Thomas Köppe authored Dec 28, 2022
  82be8a1d
- [InstSimplify] add tests for div exact; NFC · 935a6525
  Sanjay Patel authored Dec 28, 2022
  
  935a6525
- [InstCombine] add tests for udiv-by-constant demanded bits; NFC · 7f0c1150
  Sanjay Patel authored Dec 28, 2022
  
  7f0c1150
- [NVPTX] Emit .noreturn directive · fa023e0f
  Pavel Kopyl authored Dec 28, 2022
  fa023e0f
- Handle simple diamond CFG hoisting in DivRemPairs. · 88e85aa5
  Owen Anderson authored Dec 23, 2022
  88e85aa5
- [InstCombine] preserve signbit semantics of NAN with fold to fabs · 862e35e2
  Sanjay Patel authored Dec 28, 2022
  862e35e2
- [SLP]Use ShuffleInstructionBuilder for vector shrinking. · ac01ae71
  Alexey Bataev authored Dec 21, 2022
  ac01ae71
- [NFC][exegesis] By default, don't dump objects to disk · 498704d5
  Roman Lebedev authored Dec 28, 2022
  498704d5
- Fix failure of ldst-16-byte.mir · d0068087
  Qiu Chaofan authored Dec 28, 2022
  
  d0068087
- [PowerPC] Enable track-subreg-liveness by default · 0ad57bf2
  Qiu Chaofan authored Dec 28, 2022
  0ad57bf2
- [MC][BPF] Add bpf guard for MC test data-section-prefix.ll · 5922d361
  Yonghong Song authored Dec 27, 2022
  5922d361
- [SCEV] Properly clean up duplicated FoldCacheUser ID entries. · a5640488
  Florian Hahn authored Dec 28, 2022
  a5640488
- MC: Add .data. and .rodata. prefixes to MCContext section classification · f27c4903
  Dave Marchevsky authored Dec 27, 2022
  f27c4903