Commits · e980913831c1dfe5ce443a0b4f7a551c992133b8 · Roger Ferrer / llvm-epi · GitLab

Jul 29, 2020
- [Tests] Split a file for ease of update · e9809138
  Philip Reames authored Jul 29, 2020
  
  e9809138
- [AMDGPU] prefer non-mfma in post-RA schedule · 13b63be4
  Stanislav Mekhanoshin authored Jul 29, 2020
  13b63be4
- [PowerPC] Add options to control paired vector memops support · 7aaa8562
  Baptiste Saleil authored Jul 28, 2020
  7aaa8562
- [GlobalISel] Add G_INTRINSIC_LRINT and translate from llvm.lrint · 0c0e3606
  Amara Emerson authored Jul 24, 2020
  0c0e3606
- [AArch64][GlobalISel] Selection support for vector DUP[X]lane instructions. · d8ba6222
  Amara Emerson authored Jul 29, 2020
  d8ba6222
- AMDGPU/GlobalISel: Handle llvm.amdgcn.reloc.constant · 59fac51f
  Matt Arsenault authored Jul 21, 2020
  
  59fac51f
- GlobalISel: Implement lower for G_EXTRACT_VECTOR_ELT · 0b7de796
  Matt Arsenault authored Jul 26, 2020
  0b7de796
- [AArch64][GlobalISel] Select XRO addressing mode with wide immediates · 7ff95755
  Jessica Paquette authored Jul 28, 2020
  7ff95755
- AMDGPU: Relax restriction on folding immediates into physregs · 766cb615
  Matt Arsenault authored Jul 19, 2020
  766cb615
- [WebAssembly] Fix getBottom for loops · 276f9e8c
  Heejin Ahn authored Jul 29, 2020
  276f9e8c
- [X86] Add custom lowering for llvm.roundeven with sse4.1. · c4823b24
  Craig Topper authored Jul 29, 2020
  c4823b24
- [DAG][AMDGPU][X86] Add SimplifyMultipleUseDemandedBits handling for... · fdc90277
  Simon Pilgrim authored Jul 29, 2020
  fdc90277
- [PowerPC] Set v1i128 to expand for SETCC to avoid crash · 802c0430
  Kang Zhang authored Jul 29, 2020
  802c0430
- [Statepoint] When using the tied def lowering, unconditionally use vregs [almost NFC] · 31342eb6
  Philip Reames authored Jul 29, 2020
  31342eb6
- [MachineVerifier] Handle the PHI node for verifyLiveVariables() · a4ade9ed
  Kang Zhang authored Jul 29, 2020
  a4ade9ed
- AMDGPU: Account for the size of LDS globals used through constant · d42c7b22
  Matt Arsenault authored Jul 17, 2020
  d42c7b22
- [MachineCopyPropagation] BackwardPropagatableCopy: add check for hasOverlappingMultipleDef · 6a05c6bf
  Simon Wallis authored Jul 29, 2020
  6a05c6bf
- [SVE][CodeGen] Add simple integer add tests for SVE tuple types · 20787717
  David Sherwood authored Jul 16, 2020
  20787717
- [ARM] Optimize immediate selection · 85342c27
  Sjoerd Meijer authored Jul 29, 2020
  85342c27
- AMDGPU: Make saturating add/sub legal for DAG path · c230965c
  Matt Arsenault authored Jul 13, 2020
  
  c230965c
- AMDGPU/GlobalISel: Select llvm.amdgcn.global.atomic.csub · cdd45d5f
  Matt Arsenault authored Jul 21, 2020
  cdd45d5f
- [SVE] Add checks for no warnings in CodeGen/AArch64/sve-sext-zext.ll · f43b5c7a
  David Sherwood authored Jul 03, 2020
  f43b5c7a
- [X86][SSE] getV4X86ShuffleImm8 - canonicalize broadcast masks · 0c005be6
  Simon Pilgrim authored Jul 29, 2020
  0c005be6
- [Hexagon] Correct the order of operands when lowering funnel shift-left · d50d4c3d
  Ikhlas Ajbar authored Jul 28, 2020
  d50d4c3d
- AMDGPU: Optimize copies to exec with other insts after exec def · 44211f20
  Matt Arsenault authored Jul 23, 2020
  44211f20
- AMDGPU/GlobalISel: Fix selecting llvm.amdgcn.s.getreg · b6ebc773
  Matt Arsenault authored Jul 25, 2020
  b6ebc773
- [WebAssembly] Remove intrinsics for SIMD widening ops · 11bb7eef
  Thomas Lively authored Jul 28, 2020
  11bb7eef
- [X86] Add FeatureCMPXCHG8B and FeatureSlowUAMem16 to 'lakemont' in X86.td · 06cf6f77
  Craig Topper authored Jul 28, 2020
  06cf6f77
- [WebAssembly] Implement truncating vector stores · ffd8c23c
  Thomas Lively authored Jul 28, 2020
  ffd8c23c
- AMDGPU: Don't assume call targets are registers · 068808d1
  Matt Arsenault authored Jul 25, 2020
  068808d1
- AMDGPU: Handle a few missing cases in getAddrModeArguments · 8860daf0
  Matt Arsenault authored Jul 21, 2020
  
  8860daf0
- AMDGPU: Don't assume there is only one terminator copy · b3e63aa8
  Matt Arsenault authored Jul 23, 2020
  b3e63aa8
- AMDGPU: Fix verifier error on spilling partially defined SGPRs · 592f2e8d
  Matt Arsenault authored Jul 23, 2020
  592f2e8d
- AMDGPU: Serialize MFI spill fields · 66d60e06
  Matt Arsenault authored Jul 23, 2020
  66d60e06
Jul 28, 2020
- AMDGPU/GlobalISel: Add some missing tests for extract selection · ee713a2d
  Matt Arsenault authored Jul 26, 2020
  
  ee713a2d
- AMDGPU: Check for other defs when folding conditions into s_andn2_b64 · e9b236f4
  Matt Arsenault authored Jul 24, 2020
  e9b236f4
- [X86] Remove disabled miscompiling X86CondBrFolding pass · e1dd212c
  Roman Lebedev authored Jul 28, 2020
  e1dd212c
- [DAG] isSplatValue - add support for TRUNCATE/SIGN_EXTEND/ZERO_EXTEND · b4b6e774
  Simon Pilgrim authored Jul 28, 2020
  b4b6e774
- [X86][XOP] Shuffle v16i8 using VPPERM(X,Y) instead of OR(PSHUFB(X),PSHUFB(Y)) · 4838cd46
  Simon Pilgrim authored Jul 28, 2020
  
  4838cd46
- [AMDGPU] Spill CSR VGPR which is reserved for SGPR spills · adeeac9d
  Austin Kerbow authored Jul 13, 2020
  adeeac9d