Commits · ea6171c108c47c1ee486388adfa106e13e280e33 · Roger Ferrer / llvm-epi · GitLab

May 26, 2022
- [MachineSink] replace MachineLoop with MachineCycle · d7927523
  Chen Zheng authored Apr 19, 2022
  d7927523
- [FileCheck] Catch missspelled directives. · ad1d60c3
  Ivan Kosarev authored May 26, 2022
  ad1d60c3
- [X86] Add non-uniform vector tests for 'one bit diff' comparison fold · b45e0468
  Simon Pilgrim authored May 26, 2022
  
  b45e0468
- [llvm][DWARF] Move test using X86 triple into X86 tests · 38eb4fe7
  David Spickett authored May 26, 2022
  38eb4fe7
- [LegalizeTypes][VP] Add widen and split support for VP_TRUNCATE · 8aa6b05d
  Lian Wang authored May 19, 2022
  8aa6b05d
- [RISCV][NFC] Remove solved TODO for combining constant shifts · 085acede
  Haocong.Lu authored May 26, 2022
  085acede
May 25, 2022
- Round up zero-sized symbols to 1 byte in `.debug_aranges`. · 256a52d9
  Patrick Walton authored May 25, 2022
  256a52d9
- [riscv] Remove mutation of prior vsetvli from insertion dataflow · be2cb824
  Philip Reames authored May 25, 2022
  be2cb824
- AMDGPU/GISel: Factor out AMDGPURegisterBankInfo::buildReadFirstLane · affa1b1c
  Nicolai Hähnle authored May 10, 2022
  affa1b1c
- Revert "AMDGPU/GISel: Factor out AMDGPURegisterBankInfo::buildReadFirstLane" · afc90101
  Nicolai Hähnle authored May 25, 2022
  afc90101
- AMDGPU/GISel: Factor out AMDGPURegisterBankInfo::buildReadFirstLane · 2a28467e
  Nicolai Hähnle authored May 10, 2022
  2a28467e
- Allow pointer types for atomicrmw xchg · 18e6b823
  Takafumi Arakaki authored May 25, 2022
  18e6b823
- [RISCV] Preserve fast math flags in lowerVPOp. · 172149e9
  Craig Topper authored May 25, 2022
  172149e9
- [X86] Add isSimple check to the load combine in combineExtractVectorElt. · 06fee478
  Craig Topper authored May 25, 2022
  06fee478
- [RISCV] Hoist VSETVLI vlmax, vtype out of scalable loops · 2a3b6f2c
  Philip Reames authored May 25, 2022
  2a3b6f2c
- [riscv] Add coverage for fixed length vector loops using LMUL · a4a438f0
  Philip Reames authored May 25, 2022
  
  a4a438f0
- [VP][fix] Don't discard masks in reductions · 6e127110
  Simon Moll authored May 25, 2022
  6e127110
- [x86] add test with volatile load; NFC · d5ebba2a
  Sanjay Patel authored May 25, 2022
  d5ebba2a
- [ARM] Fix vcvtb/t.f16 input liveness · 18cb3b35
  David Green authored May 25, 2022
  18cb3b35
- [RISCV] Add pre-emit pass to make more instructions compressible · 29a5a7c6
  Lewis Revill authored Apr 25, 2022
  29a5a7c6
- [RISCV] Fix vnsrl/vnsra isel patterns that are dropping VL. · 66db5312
  Craig Topper authored May 24, 2022
  66db5312
- Revert "[MachineSink] replace MachineLoop with MachineCycle" · 80c4910f
  Chen Zheng authored May 24, 2022
  80c4910f
- [RISCV] Ensure the forwarded AVL register is alive · 948d9313
  Philip Reames authored May 24, 2022
  948d9313
May 24, 2022
- [RISCV] Hoist VSETVLI out of idiomatic fixed length vector loops · a95ecb20
  Philip Reames authored May 24, 2022
  a95ecb20
- [SelectionDAG] Add support to widen ISD::STEP_VECTOR operations. · 6f215ca6
  Paul Walker authored May 22, 2022
  6f215ca6
- Recommit "[SelectOpti][5/5] Optimize select-to-branch transformation" · 67be40df
  Sotiris Apostolakis authored May 23, 2022
  67be40df
- [AMDGPU] Disable newly added gfx90a global isel image tests. NFC. · 26c4cf23
  Stanislav Mekhanoshin authored May 24, 2022
  26c4cf23
- [AMDGPU] Enforce alignment of image vaddr on gfx90a · 5df6669d
  Stanislav Mekhanoshin authored May 18, 2022
  5df6669d
- Recommit "[RISCV] Use selectShiftMaskXLen ComplexPattern for isel of rotates." · 415b9f59
  Craig Topper authored May 24, 2022
  415b9f59
- [RISCV] Add test cases showing failure to remove mask on rotate amounts. · cddeb78e
  Craig Topper authored May 24, 2022
  cddeb78e
- Fix behavior of is_fp_class on empty class set · 6fc0bc5b
  Serge Pavlov authored May 24, 2022
  6fc0bc5b
- [DAG] Unroll vectorized FPOW instructions before widening that will scalarize to libcalls anyway · 11455e47
  Simon Pilgrim authored May 24, 2022
  11455e47
- [x86][DAG] Unroll vectorized FREMs that will become libcalls · 8b5d9cbb
  Nabeel Omer authored May 24, 2022
  8b5d9cbb
- [X86] scalar_widen_div.ll - remove non-generated CHECKs · 96323c9f
  Simon Pilgrim authored May 24, 2022
  96323c9f
- [X86] Add test showing failure to expand <2 x float> fpow without widening to <4 x float> · 64186e9b
  Simon Pilgrim authored May 24, 2022
  64186e9b
- [RISCV] Ensure the entire stack is aligned to the RVV stack alignment · 08c9fb84
  Fraser Cormack authored May 19, 2022
  08c9fb84
- [RISCV] Fix RVV stack frame alignment bugs · cb8681a2
  Fraser Cormack authored May 16, 2022
  cb8681a2
- [X86][AMX] Multiple configure for AMX register. · 496156ac
  Luo, Yuanke authored May 03, 2022
  496156ac
- [MachineSink] replace MachineLoop with MachineCycle · 62a9b36f
  Chen Zheng authored Apr 19, 2022
  62a9b36f
- Revert "[SelectOpti][5/5] Optimize select-to-branch transformation" · 1786e70b
  Sotiris Apostolakis authored May 24, 2022
  1786e70b