Commits · eb97e3554c695e3d0005ab1d360c99a77af5aaf4 · Roger Ferrer / llvm-epi · GitLab

Oct 25, 2016
- Add option to specify minimum number of entries for jump tables · eb97e355
  Evandro Menezes authored Oct 25, 2016
  eb97e355
- Switch lowering: improve partitioning of jump tables · 601f4cb9
  Evandro Menezes authored Oct 25, 2016
  601f4cb9
- [WebAssembly] Add immediate fields to call_indirect and memory operators. · f50d964b
  Dan Gohman authored Oct 25, 2016
  f50d964b
- [SystemZ] Do not use LOC(G) for volatile loads · 7bdb485e
  Ulrich Weigand authored Oct 25, 2016
  7bdb485e
- [X86][SSE] Add support for (V)PMOVSX* constant folding · 5c3c9707
  Simon Pilgrim authored Oct 25, 2016
  5c3c9707
- [DAGCombine] Preserve shuffles when one of the vector operands is constant · 124470a2
  Zvi Rackover authored Oct 25, 2016
  124470a2
- [AVX-512] Add support for creating SIGN_EXTEND_VECTOR_INREG and... · 01e4667e
  Craig Topper authored Oct 25, 2016
  01e4667e
Oct 24, 2016
- [SelectionDAG] Update ComputeNumSignBits SRA/SHL handlers to accept scalar or vector splats · e3e6585c
  Simon Pilgrim authored Oct 24, 2016
  e3e6585c
- [x86] add tests for {-1,0,1} select of constants · 87eea107
  Sanjay Patel authored Oct 24, 2016
  87eea107
- [llvm] Remove redundant --check-prefix=CHECK from tests · da99e33a
  Mandeep Singh Grang authored Oct 24, 2016
  da99e33a
- [PPC] Generate positive FP zero using xor insn instead of loading from constant area · c90b02cf
  Ehsan Amiri authored Oct 24, 2016
  c90b02cf
- Revert r284580+r284917. ("Synthesize TBB/TBH instructions") · b37864b5
  Eli Friedman authored Oct 24, 2016
  b37864b5
- [AArch64] Optionally use the Newton series for reciprocal estimation · eff2bd9d
  Evandro Menezes authored Oct 24, 2016
  eff2bd9d
- [PPC] Better codegen for AND, ANY_EXT, SRL sequence · 1f31e915
  Ehsan Amiri authored Oct 24, 2016
  1f31e915
- [x86] regenerate checks · 7b12e367
  Sanjay Patel authored Oct 24, 2016
  7b12e367
- AMDGPU: Fix Two Address problems with v_movreld · a785209b
  Nicolai Haehnle authored Oct 24, 2016
  a785209b
- [AVX-512] Remove masked pmin/pmax intrinsics and autoupgrade to native IR. · 8ec5c732
  Craig Topper authored Oct 24, 2016
  8ec5c732
- [DAG] enhance computeKnownBits to handle SRL/SRA with vector splat constant · 9ca028c2
  Sanjay Patel authored Oct 23, 2016
  9ca028c2
Oct 22, 2016
- [X86][AVX512VL] Added support for combining target 256-bit shuffles to AVX512VL VPERMV3 · d3829c89
  Simon Pilgrim authored Oct 22, 2016
  d3829c89
- [X86][AVX512] Added support for combining target shuffles to AVX512 VPERMV3 · 56c0524f
  Simon Pilgrim authored Oct 22, 2016
  56c0524f
- [ARM] Fix crash in ConstantIslands · 2bae8640
  James Molloy authored Oct 22, 2016
  2bae8640
- [X86] Apply the Update LLC Test Checks tool on the mmx-bitcast test · 8eb99d88
  Zvi Rackover authored Oct 22, 2016
  8eb99d88
- [X86] Add support for printing shuffle comments for VALIGN instructions. · b084c90a
  Craig Topper authored Oct 22, 2016
  b084c90a
- [x86] add test for missing vector SRA combine via computeKnownBits · 5b7767f6
  Sanjay Patel authored Oct 21, 2016
  5b7767f6
Oct 21, 2016
- AMDGPU/SI: Fix crash caused by r284267 · 6c7dd980
  Tom Stellard authored Oct 21, 2016
  6c7dd980
- [DAG] enhance computeKnownBits to handle SHL with vector splat constant · ca92c36e
  Sanjay Patel authored Oct 21, 2016
  ca92c36e
- X86: Improve BT instruction selection for 64-bit values. · e9bd4982
  Peter Collingbourne authored Oct 21, 2016
  e9bd4982
- [X86][AVX512BWVL] Added support for lowering v16i16 shuffles to AVX512BWVL vpermw · ab488723
  Simon Pilgrim authored Oct 21, 2016
  ab488723
- [X86][AVX512BWVL] Added support for combining target v16i16 shuffles to AVX512BWVL vpermw · da814cba
  Simon Pilgrim authored Oct 21, 2016
  da814cba
- [X86][AVX512] Added support for combining target shuffles to AVX512... · 0109bf11
  Simon Pilgrim authored Oct 21, 2016
  0109bf11
- [DAG] fold negation of sign-bit · 81029f6a
  Sanjay Patel authored Oct 21, 2016
  81029f6a
- [x86] add tests for potential negation folds · 97de8a4c
  Sanjay Patel authored Oct 21, 2016
  97de8a4c
- [Hexagon] Handle spills of partially defined double vector registers · b71085b5
  Krzysztof Parzyszek authored Oct 21, 2016
  b71085b5
- [WebAssembly] Fix for 0xc call_indirect changes · 6f69783f
  Derek Schuff authored Oct 21, 2016
  6f69783f
- [X86][SSE] Regenerated sext/zext constant folding tests and added i686 tests · 372e916a
  Simon Pilgrim authored Oct 21, 2016
  372e916a
- [X86][SSE] Regenerated chained pmovsx store tests and added i686 tests · 098bd728
  Simon Pilgrim authored Oct 21, 2016
  098bd728
- [DAG] use SDNode flags 'nsz' to enable fadd/fsub with zero folds · cbaba93c
  Sanjay Patel authored Oct 21, 2016
  cbaba93c
- [X86][AVX512] Add mask/maskz writemask support to subvector broadcast shuffle decode comments · 32b06235
  Simon Pilgrim authored Oct 21, 2016
  32b06235
- [X86][AVX] Add 32-bit target tests for vector lzcnt/tzcnt to demonstrate... · f447fbf9
  Simon Pilgrim authored Oct 21, 2016
  f447fbf9
- Fix WebAssembly test after r284757. · 0d41eb8c
  Benjamin Kramer authored Oct 21, 2016
  0d41eb8c