Commits · ec35a2f6e9dc79a8d98a580eb6dfa03da3a3c760 · Roger Ferrer / llvm-epi · GitLab

Sep 15, 2022
- [RISCV] Add test coverage for mixed fixed and scalable uses of splats · ec35a2f6
  Philip Reames authored Sep 15, 2022
  
  ec35a2f6
- [CGP,AArch64] Replace zexts with shuffle that can be lowered using tbl. · 81a11da7
  Florian Hahn authored Sep 15, 2022
  81a11da7
- [IntegerDivision][AMDGPU] Use CreateLogicalOr to block poison propagation. · ace05124
  Craig Topper authored Sep 15, 2022
  ace05124
- [AMDGPU] Add GFX11 ds_bvh_stack_rtn_b32 instruction · 3822a01e
  Jay Foad authored Sep 15, 2022
  3822a01e
- AMDGPU: Use GlobalPriority for largest register tuples · 69153d6c
  Matt Arsenault authored Jul 23, 2022
  69153d6c
- [AArch64][SME] Fix lowering of llvm.aarch64.get.pstatesm() · 45d28779
  Sander de Smalen authored Sep 14, 2022
  45d28779
- [AArch64] Add big-endian tests for trunc-to-tbl.ll · 791a7ae1
  Florian Hahn authored Sep 15, 2022
  791a7ae1
- [AArch64] Add big-endian tests for zext-to-tbl.ll · 8f19de84
  Florian Hahn authored Sep 15, 2022
  8f19de84
- [AMDGPU][SILoadStoreOptimizer] Merge SGPR_IMM scalar buffer loads. · 693f8162
  Ivan Kosarev authored Sep 15, 2022
  693f8162
- [SPIRV] add IR regularization pass · 3544d200
  Ilia Diachkov authored Sep 14, 2022
  3544d200
- [PowerPC] Converts to comparison against zero even when the optimization · 6e0e926c
  esmeyi authored Sep 15, 2022
  6e0e926c
- [GlobalISel][AArch64] Fix pcsections for expanded atomics and add more tests · 72e7575f
  Marco Elver authored Sep 15, 2022
  72e7575f
- [M68k] Fix the crash of fast register allocator · bea33f75
  Sheng authored Sep 15, 2022
  bea33f75
Sep 14, 2022
- [DAGCombiner] More load-store forwarding for big-endian · 207228c1
  Roland Froese authored Sep 14, 2022
  207228c1
- [AMDGPU] Check for num elts in SelectVOP3PMods · abd927e5
  Piotr Sobczak authored Sep 14, 2022
  abd927e5
- [LLVM][AArch64] Don't warn about clobbering X16 when Speculative Load Hardening is used · 3acaf040
  David Spickett authored Sep 13, 2022
  3acaf040
- [AArch64] Disable nontemproal load for Big Endian · d1dec04d
  Zain Jaffal authored Sep 14, 2022
  d1dec04d
- [AArch64] Add nontemporal load tests for big endian. · 244a6a76
  Zain Jaffal authored Sep 14, 2022
  244a6a76
- [MIR] Support printing and parsing pcsections · 4627a30a
  Marco Elver authored Sep 14, 2022
  4627a30a
- [amdgpu] Expand all ConstantExpr users of LDS variables in instructions · cdb97389
  Jon Chesterfield authored Sep 14, 2022
  cdb97389
- [NVPTX] Use MBB.begin() instead MBB.front() in NVPTXFrameLowering::emitPrologue · e2632fbc
  Shivam Gupta authored Sep 11, 2022
  e2632fbc
- [RISCV] Transform VMERGE_VVM_<LMUL>_TU with all ones mask to VADD_VI_<LMUL>_TU. · 1b56b2b2
  Yeting Kuo authored Sep 13, 2022
  1b56b2b2
- [RISCV] Lower BUILD_VECTOR to RISCVISD::VID_VL if it is floating-point type. · dd53a0bb
  Han-Kuan Chen authored Sep 12, 2022
  dd53a0bb
- [WebAssembly] Improve codegen for shuffles with undefined lane indices · 28557e8c
  Fanchen Kong authored Sep 13, 2022
  28557e8c
- RegisterCoalescer: Fix verifier error when merging copy of undef · d00b0aab
  Matt Arsenault authored Jun 07, 2022
  d00b0aab
- [RISCV] Add MIR comments for VecPolicy operands · 09d73fe8
  Philip Reames authored Sep 13, 2022
  09d73fe8
Sep 13, 2022
- [DirectX backend] Remove Attribute not for DXIL on CallInst · 1e3d4c43
  Xiang Li authored Sep 04, 2022
  1e3d4c43
- [AMDGPU] Don't shrink VOP3 instructions pre-RA on GFX10+ · 2e8863b6
  Jay Foad authored Sep 13, 2022
  2e8863b6
- [SelectOpti] Fix lifetime intrinsic bug · eda61fb6
  Sotiris Apostolakis authored Sep 13, 2022
  eda61fb6
- [RISCV] Split vmerge peephole tests so they can be auto-gened · c97952ee
  Philip Reames authored Sep 13, 2022
  c97952ee
- [RISCV] Teach lowerVECTOR_SHUFFLE to recognize some shuffles as vnsrl. · 8d7e73ef
  Craig Topper authored Sep 13, 2022
  8d7e73ef
- [LegalizeTypes][NVPTX] Remove extra compare from fallback code for ISD::ADD in ExpandIntRes_ADDSUB. · efd5acf1
  Craig Topper authored Sep 13, 2022
  efd5acf1
- [RISCV] Return true in hasBitTest when Zbs is enabled and update BEXTI pattern... · 54716084
  Alex Bradbury authored Sep 13, 2022
  54716084
- [RISCV] Fix a bug in i32 FP_TO_UINT_SAT lowering on RV64. · 5224bae6
  Craig Topper authored Sep 13, 2022
  5224bae6
- [AArch64] Sink splat(s/zext(..)) to uses · 993b203b
  David Green authored Sep 13, 2022
  993b203b
- [X86] Add GFNI test coverage for bitreverse codegen · 8bf04e9f
  Simon Pilgrim authored Sep 13, 2022
  8bf04e9f
- [llvm][AArch64] Explain why certain registers are reserved on Arm64EC · 0b8a4438
  David Spickett authored Sep 12, 2022
  0b8a4438
- [AMDGPU] Add GFX11 globalisel test coverage for fptosi/fptoui · 3743f9af
  Jay Foad authored Sep 13, 2022
  
  3743f9af
- [TypePromotionPass] Don't treat phi's as ToPromote · f124e59b
  David Green authored Sep 13, 2022
  f124e59b
- Move ExpandLargeDivRem to llvm/test/CodeGen/X86 because they need a triple · 6bf1b4e8
  Matthias Gehre authored Sep 13, 2022
  
  6bf1b4e8