Commits · ee544b8d868d5845798c37200a4b2bd9de889a96 · Roger Ferrer / llvm-epi · GitLab

May 27, 2021
- [NFC][X86][Codegen] Re-autogenerate a few tests to reduce noise in future changes · ee544b8d
  Roman Lebedev authored May 28, 2021
  
  ee544b8d
- [PowerPC] Added multiple PowerPC builtins · 62b5df7f
  Quinn Pham authored May 27, 2021
  62b5df7f
- [RISCV] Fix typo, use addImm instead of addReg. · 020df692
  Craig Topper authored May 27, 2021
  
  020df692
- [x86] add tests for extend of vector compare; NFC · 0d5219fe
  Sanjay Patel authored May 27, 2021
  
  0d5219fe
- [NFC][X86][Codegen] vector-interleaved-store-i16-stride-5.ll: precisely match the actual IR · 9712b167
  Roman Lebedev authored May 27, 2021
  9712b167
- [RISCV] Add a test showing missed opportunity to avoid a vsetvli in a loop. · d7ae2438
  Craig Topper authored May 27, 2021
  d7ae2438
- [NFC][X86][Codegen] Re-autogenerate check lines in a few tests to remove noise from future changes · bafbec85
  Roman Lebedev authored May 27, 2021
  
  bafbec85
- [RISCV] Teach vsetvli insertion to use vsetvl x0, x0 form when we can tell... · 527cd013
  Craig Topper authored May 27, 2021
  527cd013
- [X86] Fold (shift undef, X)->0 for vector shifts by immediate. · a105d302
  Craig Topper authored May 27, 2021
  a105d302
- [X86] Pre-commit tests for D103192. NFC · b5f8ac26
  Craig Topper authored May 27, 2021
  
  b5f8ac26
- [RISCV] Add a test case showing incorrect call-conv lowering · 6f4794fe
  Fraser Cormack authored May 27, 2021
  6f4794fe
- GlobalISel: Do not change register types in lowerLoad · e892705d
  Matt Arsenault authored May 18, 2021
  e892705d
- AMDGPU/GlobalISel: Fix broken test run line · 34046de0
  Matt Arsenault authored May 20, 2021
  
  34046de0
- [X86][SSE] Regenerate some tests to expose the rip relative vector/broadcast loads · e49d6e16
  Simon Pilgrim authored May 26, 2021
  
  e49d6e16
- VirtRegMap: Preserve LiveDebugVariables · 808dc6f8
  Matt Arsenault authored Oct 29, 2018
  808dc6f8
- AMDGPU/GlobalISel: Lower constant-32-bit zextload/sextload consistently · ee359000
  Matt Arsenault authored May 18, 2021
  ee359000
- [DAGCombine][RISCV] Don't try to trunc-store combined vector stores · b7101e21
  Fraser Cormack authored May 26, 2021
  b7101e21
- [RISCV] Allow passing fixed-length vectors via the stack · 8c73a31c
  Fraser Cormack authored May 13, 2021
  8c73a31c
- [ARM] Extra test for reverted WLS memset. NFC · 1d5b976b
  David Green authored May 27, 2021
  
  1d5b976b
- [SelectionDAG][RISCV] Don't unroll 0/1-type bool VSELECTs · 772b58a6
  Fraser Cormack authored May 26, 2021
  772b58a6
- [AMDGPU][GlobalISel] Allow amdgpu_gfx calling conv · 0bb60dbe
  Sebastian Neubauer authored May 26, 2021
  0bb60dbe
- [GlobalISel] Implement splitting of G_SHUFFLE_VECTOR. · 9f39ba13
  Amara Emerson authored May 19, 2021
  9f39ba13
- [GlobalISel] Don't emit lost debug location remarks when legalizing tail calls · 324af79d
  Jessica Paquette authored May 25, 2021
  324af79d
- [AArch64][GlobalISel] Legalize non-power-of-2 vector elements for G_STORE. · 74edfb28
  Amara Emerson authored May 26, 2021
  74edfb28
- [Hexagon] Restore handling of expanding shuffles · 002f5e15
  Krzysztof Parzyszek authored May 22, 2021
  002f5e15
May 26, 2021
- [RISCV] Use X0 as destination of inserted vsetvli when possible. · fdf10e61
  Craig Topper authored May 26, 2021
  fdf10e61
- [NFC][Codegen][X86] Add a few more interleaved load/store patterns w/ i16 element type · ab7f26dc
  Roman Lebedev authored May 26, 2021
  ab7f26dc
- [AMDGPU] Fix kernel LDS lowering for constants · 5e2facb9
  Stanislav Mekhanoshin authored May 26, 2021
  5e2facb9
- [RISCV] Optimize SEW=64 shifts by splat on RV32. · 9065118b
  Craig Topper authored May 26, 2021
  9065118b
- [RISCV] Remove --riscv-no-aliases from RVV tests · d63d662d
  Jessica Clarke authored May 26, 2021
  d63d662d
- [RISCV] Don't propagate VL/VTYPE across inline assembly in the Insert VSETVLI pass. · b2c7ac87
  Craig Topper authored May 26, 2021
  b2c7ac87
- [RISCV] Enable cross basic block aware vsetvli insertion · 1b47a3de
  Craig Topper authored May 25, 2021
  1b47a3de
- [SystemZ] Support i128 inline asm operands. · d058262b
  Jonas Paulsson authored Apr 19, 2021
  d058262b
- [AMDGPU] Fix function pointer argument bug in AMDGPU Propagate Attributes pass. · fcd32d62
  jweightma authored May 26, 2021
  fcd32d62
- [X86][AMX] Fix a bug on tile config. · 4ed2b6cc
  Luo, Yuanke authored May 26, 2021
  4ed2b6cc
- [ARM] Extra test for reverted WLS memset. NFC · a409fcdd
  David Green authored May 26, 2021
  
  a409fcdd
- [X86][SSE] Regenerate some tests to expose the rip relative vector/broadcast loads · 629e2b34
  Simon Pilgrim authored May 26, 2021
  
  629e2b34
- [AArch64] Generate LD1 for anyext i8 or i16 vector load · 8ac66d61
  Andrew Savonichev authored May 05, 2021
  8ac66d61
- [MC] Move elf-unique-sections-by-flags.ll to X86/ · ab8c4411
  Tomas Matheson authored May 26, 2021
  
  ab8c4411
- [MC][ELF] Emit unique sections for different flags · 165321b3
  Tomas Matheson authored May 12, 2021
  165321b3