Commits · ee71c1bbccb19ed7a30b9aaf112a2c6ac2987193 · Roger Ferrer / llvm-epi · GitLab

Jul 14, 2021
- [X86] Implement smarter instruction lowering for FP_TO_UINT from f32/f64 to... · ee71c1bb
  Simon Pilgrim authored Jul 14, 2021
  ee71c1bb
- [gn build] Port c08dabb0 · 90e7f5d2
  LLVM GN Syncbot authored Jul 14, 2021
  
  90e7f5d2
- Revert rGb803294cf78714303db2d3647291a2308347ef23 : "[InstCombine] Fold... · 0722f3d0
  Simon Pilgrim authored Jul 14, 2021
  0722f3d0
- [gn build] (manually) merge 462d4de3 · aff09545
  Nico Weber authored Jul 14, 2021
  
  aff09545
- [NFC][PowerPC] Added test to check regsiter allocation for ACC registers · cf0aa0b6
  Stefan Pintilie authored Jul 13, 2021
  cf0aa0b6
- [DebugInfo] Correctly update dbg.values with duplicated location ops · 810e4c3c
  Stephen Tozer authored Jul 13, 2021
  810e4c3c
- [InstCombine] Fold (select C, (gep Ptr, Idx), Ptr) -> (gep Ptr, (select C, Idx, 0)) (PR50183) · b803294c
  Simon Pilgrim authored Jul 13, 2021
  b803294c
- [RISCV] Fix the neutral element in vector 'fadd' reductions · 03a4702c
  Fraser Cormack authored Jul 13, 2021
  03a4702c
- [AMDGPU] Init scratch only if necessary · 4359b870
  Sebastian Neubauer authored Jul 14, 2021
  4359b870
- [AMDGPU] Precommit flat-scratch-init.ll test · a12e5518
  Sebastian Neubauer authored Jul 13, 2021
  
  a12e5518
- [AArch64][SME] Add matrix register definitions and parsing support · c08dabb0
  Cullen Rhodes authored Jul 14, 2021
  c08dabb0
- [AMDGPU] Don't handle export done when unify exit nodes · d9b9fdd9
  Ruiling Song authored Jul 08, 2021
  d9b9fdd9
- [NFC][AMDGPU] autogenerate kill-infinite-loop.ll checks · 1d9585c8
  Ruiling Song authored Jul 08, 2021
  1d9585c8
- [RegisterCoalescer] Resolve conflict based on liveness of subregister · 40e3df2a
  Ruiling Song authored Jun 18, 2021
  40e3df2a
- Reformulate OrcJIT tutorial doc to make it more clear. · 8ae31b08
  Yuichi Yoshida authored Jul 14, 2021
  8ae31b08
- [AIX] Update testcase to use aix triple · 64785ac1
  Jinsong Ji authored Jul 14, 2021
  64785ac1
- [CSSPGO][llvm-profgen] Fix a missing initalization · 6b04ecaa
  Hongtao Yu authored Jul 13, 2021
  6b04ecaa
- Revert "[CSSPGO][llvm-profgen] Fix a missing initalization" · 597e9c61
  Hongtao Yu authored Jul 13, 2021
  597e9c61
- [CSSPGO][llvm-profgen] Fix a missing initalization · fef5f445
  Hongtao Yu authored Jul 13, 2021
  fef5f445
- [AbstractAttributor] Fold function calls to `__kmpc_is_spmd_exec_mode` if possible · 1100e4aa
  Shilei Tian authored Jul 13, 2021
  1100e4aa
- [SCEV] Handle zero stride correctly in howManyLessThans · 205ed009
  Philip Reames authored Jul 13, 2021
  205ed009
- [NFC][CSSPGO] Rename the name of an enum value. · cda2394d
  Hongtao Yu authored Jul 13, 2021
  
  cda2394d
- [CSSPGO] Do not import pseudo probe desc in thinLTO · 74b99b5c
  Hongtao Yu authored Jun 30, 2021
  74b99b5c
- [CSSPGO][llvm-profgen] Allow multiple executable load segments. · 07120384
  Hongtao Yu authored Jul 12, 2021
  07120384
- [AArch64] rm unused subreg's · 87c6bf92
  Jon Roelofs authored Jul 13, 2021
  
  87c6bf92
- [AArch64] Fix AArch64::dsub's size · 6377388c
  Jon Roelofs authored Jul 13, 2021
  
  6377388c
- Revert "[SCEV] Handle zero stride correctly in howManyLessThans" · 57388196
  Arthur Eubanks authored Jul 13, 2021
  57388196
- [AArch64][GlobalISel] Mark v2s64 -> v2p0 G_INTTOPTR as legal · 5bd7cc4f
  Jessica Paquette authored Jul 13, 2021
  5bd7cc4f
- AMDGPU: Try to fix test failure with EXPENSIVE_CHECKS · 3191ac27
  Matt Arsenault authored Jul 13, 2021
  3191ac27
- [NewPM][SimpleLoopUnswitch] Add option to not trivially unswitch · 0024ec59
  Arthur Eubanks authored Jul 13, 2021
  0024ec59
- RegAlloc: Allow targets to split register allocation · eebe841a
  Matt Arsenault authored Sep 27, 2018
  eebe841a
- [ScalarEvolution] Make isKnownNonZero handle more cases. · bb8c7a98
  Eli Friedman authored Jul 13, 2021
  bb8c7a98
Jul 13, 2021
- [PowerPC] Add PowerPC compare and multiply related builtins and instrinsics for XL compatibility · 18c19414
  Victor Huang authored Jul 13, 2021
  18c19414
- [WebAssembly] Run varargs codegen test with non-emscripten triple · d4e2693a
  Derek Schuff authored Jul 13, 2021
  d4e2693a
- [LLD] Adding support for RELA for CG Profile. · 24129fbc
  Alexander Yermolovich authored Jul 13, 2021
  24129fbc
- [SCEV] Handle zero stride correctly in howManyLessThans · 4df591b5
  Philip Reames authored Jul 13, 2021
  4df591b5
- [docs/llvm-cov] Document -compilation-dir · 5105a770
  Vedant Kumar authored Jul 12, 2021
  5105a770
- [NFC] Use CHECK-LABEL in trip-count-unknown-stride.ll · b28c465e
  Eli Friedman authored Jul 13, 2021
  
  b28c465e
- [LoopReroll] Add an extra defensive check to avoid SCEV assertion. · 5d1ba534
  Eli Friedman authored Jul 13, 2021
  5d1ba534
- [gn build] (manually) port 303ddb60 · 3ea8860a
  Nico Weber authored Jul 13, 2021
  
  3ea8860a