Commits · ef8707574bbc7d264644d9e6730118cc0addd871 · Roger Ferrer / llvm-epi · GitLab

Aug 24, 2021
- [AArch64][GlobalISel] Legalize narrow scalar FP arithmetic · ef870757
  Jessica Paquette authored Aug 24, 2021
  ef870757
- [AArch64][GlobalISel] Legalize + select v2p0 -> v264 G_PTRTOINT · db232de1
  Jessica Paquette authored Aug 23, 2021
  db232de1
- [AArch64][GlobalISel] Select @llvm.aarch64.neon.ld4.* · 67d4dd5c
  Jessica Paquette authored Aug 24, 2021
  67d4dd5c
- [AArch64][SME] Fix v8.6a bf16 NEON instruction predication · e9c8973f
  Cullen Rhodes authored Aug 24, 2021
  e9c8973f
- [AArch64][GlobalISel] Select @llvm.aarch64.neon.ld2.* · 2ec2b25f
  Jessica Paquette authored Aug 23, 2021
  2ec2b25f
Aug 23, 2021
- [AArch64] Correct store ReadAdrBase operand · 50f4ae58
  David Green authored Aug 23, 2021
  50f4ae58
- [AArch64][GlobalISel] Add regbankselect support for G_LLROUND · a2c8e176
  Jessica Paquette authored Aug 23, 2021
  a2c8e176
- [AArch64][GlobalISel] Legalize G_LLROUND for s64 + s32 · fe51f909
  Jessica Paquette authored Aug 23, 2021
  fe51f909
- Recommit "[LoopVectorize][AArch64] Enable ordered reductions by default for AArch64" · d024a015
  Florian Hahn authored Aug 23, 2021
  d024a015
- [AArch64][SME] Support NEON scalar FP instructions in streaming mode · fb82b836
  Cullen Rhodes authored Aug 13, 2021
  fb82b836
- [AArch64][SME] Add predicate for NEON support in streaming mode · cf3c6cca
  Cullen Rhodes authored Aug 18, 2021
  cf3c6cca
Aug 22, 2021
- [AArch64] Replace unneeded CCAssignToRegWithShadow with CCAssignToReg · 0473e9f4
  Fangrui Song authored Aug 21, 2021
  0473e9f4
Aug 21, 2021
- [AArch64][GlobalISel] Add legalizer support for the @llvm.get.dynamic.area.offset intrinsic. · 3187a4f3
  Amara Emerson authored Aug 20, 2021
  3187a4f3
- [AArch64][GlobalISel] Don't contract cross-bank copies into truncating stores. · 67bf3ac7
  Amara Emerson authored Aug 20, 2021
  67bf3ac7
Aug 20, 2021
- [AArch64][GlobalISel] Legalize non-register-sized scalar G_BITREVERSE · 9e9d7059
  Jessica Paquette authored Aug 18, 2021
  9e9d7059
- [AArch64][GlobalISel] Legalize 32-bit + narrow G_SMULO + G_UMULO · 7e91c598
  Jessica Paquette authored Aug 17, 2021
  7e91c598
- [AArch64][GlobalISel] Clamp vectors of p0 when legalizing G_LOAD/G_STORE · 16caf632
  Jessica Paquette authored Aug 20, 2021
  16caf632
- [AArch64][GlobalISel] Add regbankselect support for G_LROUND · 470c74f1
  Jessica Paquette authored Aug 19, 2021
  470c74f1
- [AArch64][GlobalISel] Mark G_LROUND as legal for s64 dst + s32/s64 src. · 44bf0dc6
  Jessica Paquette authored Aug 19, 2021
  44bf0dc6
- Revert "[LoopVectorize][AArch64] Enable ordered reductions by default for AArch64" · ab9296f1
  Florian Hahn authored Aug 20, 2021
  ab9296f1
- AArch64: don't form indexed paired ops if base reg overlaps operands. · 3d41ef68
  Tim Northover authored Aug 20, 2021
  3d41ef68
- [AArch64] Enable Upper bound unrolling universally · 94c49529
  Jingu Kang authored Jul 14, 2021
  94c49529
- [AArch64][GlobalISel] Add G_VECREDUCE fewerElements support for full scalarization. · 95ac3d15
  Amara Emerson authored Aug 18, 2021
  95ac3d15
- [AArch64][GlobalISel] Fix miscompile of <16 x s8> G_EXTRACT_VECTOR_ELT. · a0051f71
  Amara Emerson authored Aug 19, 2021
  a0051f71
Aug 19, 2021
- AArch64: copy all parts of the mem operand across when combining a store · edab411e
  Tim Northover authored Aug 19, 2021
  edab411e
- Use v16i8 rather than v2i64 as the VT for memset expansion on AArch64. · 06a4c858
  Owen Anderson authored Aug 19, 2021
  06a4c858
- [AArch64][SVE] Teach cost model that masked loads/stores are cheap · 734708e0
  Matthew Devereau authored Aug 19, 2021
  734708e0
- [LoopVectorize][AArch64] Enable ordered reductions by default for AArch64 · f4122398
  David Sherwood authored Jul 02, 2021
  f4122398
Aug 18, 2021
- [AArch64][GlobalISel] Don't allow s128 for G_ISNAN · c22b64ef
  Jessica Paquette authored Aug 18, 2021
  c22b64ef
- [AArch64][GlobalISel] Mark G_FMINNUM/G_FMAXNUM as floating point opcodes · 3d91d5b7
  Jessica Paquette authored Aug 17, 2021
  3d91d5b7
- [AArch64][GlobalISel] Legalize scalar G_FMINNUM + G_FMAXNUM · 45e1a6bd
  Jessica Paquette authored Aug 17, 2021
  45e1a6bd
- [GlobalISel] Implement lowering for G_ISNAN + use it in AArch64 · 791006fb
  Jessica Paquette authored Aug 17, 2021
  791006fb
- [Analysis][AArch64] Make fixed-width ordered reductions slightly more expensive · 219d4518
  David Sherwood authored Aug 18, 2021
  219d4518
- AArch64: compare correct type for multi-valued SDNode. · 8eb054a8
  Tim Northover authored Aug 18, 2021
  8eb054a8
- [AArch64][GlobalISel] Add support for selection of s8:fpr = G_UNMERGE <8 x s8> · 28400607
  Amara Emerson authored Aug 18, 2021
  
  28400607
- [NFC] Replace Function handling of attributes with less confusing calls · 46cf8253
  Arthur Eubanks authored Aug 16, 2021
  46cf8253
Aug 17, 2021
- [AArch64] AArch64DAGToDAGISel::tryReadRegister/tryWriteRegister - don't... · caff2aca
  Simon Pilgrim authored Aug 17, 2021
  caff2aca
- [SVE] Remove usage of getMaxVScale for AArch64, in favour of IR Attribute · ef198cd9
  Dylan Fleming authored Aug 17, 2021
  ef198cd9
- [AArch64] LowerCONCAT_VECTORS - merge getNumOperands() calls. NFCI. · 895ed640
  Simon Pilgrim authored Aug 17, 2021
  895ed640
Aug 16, 2021
- [NFC][AArch64] Fix unused var in release build · 43575620
  Jordan Rupprecht authored Aug 16, 2021
  
  43575620