Commits · f1a42300aafa437691f77b4433329d5aa14e80b3 · Roger Ferrer / llvm-epi · GitLab

May 31, 2023
- [X86] printConstant - fix asm comment issue when broadcasting from a wider constant pool entry · f1a42300
  Simon Pilgrim authored May 31, 2023
  f1a42300
- [X86] getTargetConstantBitsFromNode - ensure we truncate broadcasts from wider constants. · 65dce67f
  Simon Pilgrim authored May 31, 2023
  65dce67f
- [RISCV] Add special case for (select cc, 1.0, 0.0) to lowerSELECT · 548fa1d3
  LiaoChunyu authored May 31, 2023
  548fa1d3
- [RISCV] Add Zvfhmin extension for clang. · 35a00792
  Jianjian GUAN authored May 25, 2023
  35a00792
- [RISCV] Merge emitDirectiveOptionArchPlus and emitDirectiveOptionArchMinus... · ac1df223
  Craig Topper authored May 30, 2023
  ac1df223
- [RISCV] Strengthen some SDTypeProfiles to reduce isel table size. · 0a4ba485
  Craig Topper authored May 30, 2023
  
  0a4ba485
- [RISCV] Fix selection for some unmasked vp SDNode. · 62307f6d
  Jianjian GUAN authored May 30, 2023
  62307f6d
- [RISCV] Allow FWMUL formation for an FP extend used twice by the same multiply. · 45416335
  Craig Topper authored May 30, 2023
  
  45416335
May 30, 2023
- [AMDGPU][IGLP] Parameterize the SchedGroup processing / linking order in Solver · 1721e72d
  Jeffrey Byrnes authored Apr 27, 2023
  1721e72d
- [RISCV] Add RISCVISD::VFWMUL_VL. Use it to replace isel patterns with a DAG combine. · 463f50b4
  Craig Topper authored May 30, 2023
  463f50b4
- [RISCV][GlobalISel] Add lowerFormalArguments for calling convention · af8e3861
  Nitin John Raj authored May 30, 2023
  af8e3861
- [CodeGen] Refactor IR generation functions to use IRBuilder in ComplexDeinterleaving pass · 40a81d31
  Igor Kirillov authored Apr 19, 2023
  40a81d31
- [RISCV] Use v(f)slide1up for shuffle+insert idiom · 544a240f
  Philip Reames authored May 30, 2023
  544a240f
- [RISCV][NFC] Make Reduction scheduler resources SEW aware · d70573b1
  Michael Maitland authored May 25, 2023
  d70573b1
- [X86] Fix SunnyCove ROB/MicroOpBufferSize · 9d6f2b19
  Simon Pilgrim authored May 30, 2023
  9d6f2b19
- [X86] lowerBuildVectorAsBroadcast - remove repeated hasAVX() check. NFC. · f81f32ad
  Simon Pilgrim authored May 30, 2023
  f81f32ad
- [X86] X86FixupVectorConstantsPass - attempt to replace full width integer... · ab4b9248
  Simon Pilgrim authored May 29, 2023
  ab4b9248
- [X86] getTargetConstantBitsFromNode - support extracting fp data from ConstantDataSequential · 95661b9c
  Simon Pilgrim authored May 30, 2023
  95661b9c
- [RISCV] Generalise shouldExtendTypeInLibcall logic to apply to all <XLEN floats on soft ABIs · c4efcd69
  Alex Bradbury authored May 30, 2023
  c4efcd69
- [ms-inline asm] Add error check for `getAsInteger` · 8f386ff6
  Phoebe Wang authored May 30, 2023
  8f386ff6
- [RISCV] Teach performCombineVMergeAndVOps to handle instructions FMA instructions. · 9239d3a3
  Craig Topper authored May 29, 2023
  9239d3a3
- [RISCV] Fix unmasked vp_abs select. · 071e9d7b
  Jianjian GUAN authored May 29, 2023
  071e9d7b
May 29, 2023
- [AArch64] Remove unused declaration tryParseMRSSystemRegister · d0354892
  Kazu Hirata authored May 29, 2023
  d0354892
- [AArch64] Remove unused declaration legalizeShuffleVector · c65fd1ce
  Kazu Hirata authored May 29, 2023
  c65fd1ce
- [AArch64] Remove unused declaration LowerSCALAR_TO_VECTOR · 72c17a0d
  Kazu Hirata authored May 29, 2023
  72c17a0d
- [AMDGPU][AsmParser][NFC] Refine parsing of NamedOperandU32 operands. · a3a8cbff
  Ivan Kosarev authored May 29, 2023
  a3a8cbff
- [X86] X86FixupVectorConstantsPass - attempt to replace full width fp vector... · 98061013
  Simon Pilgrim authored May 27, 2023
  98061013
- [X86][NFC] Fix a bug after D150436 and update some comments · af55b0d7
  Wang, Xin10 authored May 28, 2023
  af55b0d7
May 28, 2023
- [ARM] Allow D-reg copies to use VMOVD with fpregs64 · 0a762ec1
  David Green authored May 28, 2023
  0a762ec1
- [Hexagon] Explicitly make vector subregs have unknown size and offset · 8a4e3675
  Krzysztof Parzyszek authored May 26, 2023
  8a4e3675
May 27, 2023
- [Hexagon] Use scalar evolution to calculate pointer difference in HVC · 96b59b4f
  Krzysztof Parzyszek authored May 26, 2023
  
  96b59b4f
- [X86] lowerBuildVectorAsBroadcast - broadcast Constant of original (BuildVector) element size · 0f8e0f42
  Simon Pilgrim authored May 24, 2023
  0f8e0f42
- [RISCV] Add isel patterns to form tail undisturbed vfwadd.wv from fpextend_vl+vfwadd_vl+vp_merge. · 28ab0322
  Craig Topper authored May 26, 2023
  28ab0322
May 26, 2023
- [RISCV] Simplify code in LowerIS_FPCLASS. NFC · 9b9e9aba
  Craig Topper authored May 26, 2023
  
  9b9e9aba
- [RISCV] Remove extra MVT::Other result from creation of RISCVISD::FCLASS_VL. · 1fea6bd8
  Craig Topper authored May 26, 2023
  
  1fea6bd8
- [RISCV] Tighten type constraint for RISCVISD::FCLASS_VL. · dcd5f312
  Craig Topper authored May 26, 2023
  
  dcd5f312
- [RISCV] Fix typo VLUpperBound to VLEN in SiFive7. NFC. · c73c7678
  Michael Maitland authored May 25, 2023
  c73c7678
- [AArch64] merge scaled and unscaled zero narrow stores. · 0c93879d
  Zain Jaffal authored May 19, 2023
  0c93879d
- [X86] fold select to mask instructions. · 969c686e
  Luo, Yuanke authored May 26, 2023
  969c686e
- [NFC] refactor code · e821db39
  Luo, Yuanke authored May 26, 2023
  e821db39