Commits · f312c1ecf4bc7003f4b10231a3147d004a39bfae · Roger Ferrer / llvm-epi · GitLab

Aug 19, 2019
- [ARM] Add support for MVE vaddv · f312c1ec
  Sam Tebbs authored Aug 19, 2019
  f312c1ec
- [ARM] MVE sext costs · 2bfc13fd
  David Green authored Aug 19, 2019
  2bfc13fd
- [X86] Teach lower1BitShuffle to match right shifts with upper zero elements on... · ebb7ddc6
  Craig Topper authored Aug 19, 2019
  ebb7ddc6
- [X86] Fix the lower1BitShuffle code added in r369215 to correctly pass the... · e47437a6
  Craig Topper authored Aug 19, 2019
  e47437a6
- [X86] Teach lower1BitShuffle to match KSHIFTR that doesn't use Zeroable and only relies on undef. · 269c6b1c
  Craig Topper authored Aug 19, 2019
  269c6b1c
- [X86] Teach lower1BitShuffle to recognize padding a subvector with zeros with... · 2eb7951d
  Craig Topper authored Aug 19, 2019
  2eb7951d
- [X86] Add a special case to LowerCONCAT_VECTORSvXi1 to handle concatenating... · 2ee46c7c
  Craig Topper authored Aug 18, 2019
  2ee46c7c
- [X86] Replace uses of getZeroVector for vXi1 vectors with DAG.getConstant. · 388b8dd9
  Craig Topper authored Aug 18, 2019
  388b8dd9
Aug 18, 2019
- [X86] Improve lower1BitShuffle handling for KSHIFTL on narrow vectors. · 9e074c06
  Craig Topper authored Aug 18, 2019
  9e074c06
- Fix signed/unsigned comparison warning. NFCI. · 63b3c56f
  Simon Pilgrim authored Aug 18, 2019
  63b3c56f
- [X86] isTargetShuffleEquivalent - add BUILD_VECTOR matching · fee2546f
  Simon Pilgrim authored Aug 18, 2019
  fee2546f
- [X86] isTargetShuffleEquivalent - early out on illegal shuffle masks. NFCI. · a66edd86
  Simon Pilgrim authored Aug 18, 2019
  a66edd86
- AMDGPU: Fix iterator error when lowering SI_END_CF · 479f3bdb
  Matt Arsenault authored Aug 18, 2019
  479f3bdb
- AMDGPU: Disambiguate v3f16 format in load/store tables · cfdc2b9b
  Matt Arsenault authored Aug 18, 2019
  cfdc2b9b
- [X86] Add a one use check to the combineStore code that handles v16i16->v16i8... · 31f829f0
  Craig Topper authored Aug 17, 2019
  31f829f0
Aug 17, 2019
- Revert Revert [AArch64InstrInfo] Stop getInstSizeInBytes returning non-zero for meta instructions. · 26295676
  Paul Walker authored Aug 17, 2019
  26295676
- Revert [AArch64InstrInfo] Stop getInstSizeInBytes returning non-zero for meta instructions. · 93c7a4a4
  Paul Walker authored Aug 17, 2019
  93c7a4a4
- Reland "[ARM] push LR before __gnu_mcount_nc" · 16fa8b09
  Jian Cai authored Aug 16, 2019
  16fa8b09
- [AArch64][GlobalISel] Fix an assertion during G_UNMERGE selection for s128 types. · 57ec292a
  Amara Emerson authored Aug 16, 2019
  57ec292a
- Revert [X86] SimplifyDemandedVectorElts - attempt to recombine target shuffle... · d0797ece
  Jordan Rupprecht authored Aug 16, 2019
  d0797ece
- [ARM] Preserve liveness in ARMConstantIslands. · eaff844f
  Eli Friedman authored Aug 16, 2019
  eaff844f
Aug 16, 2019
- [X86] Use Register/MCRegister in more places in X86 · a17d1d22
  Craig Topper authored Aug 16, 2019
  a17d1d22
- Revert "[ARM] push LR before __gnu_mcount_nc" · 2d957cfe
  Jian Cai authored Aug 16, 2019
  2d957cfe
- [ARM] push LR before __gnu_mcount_nc · f4cf3b95
  Jian Cai authored Aug 16, 2019
  f4cf3b95
- [WebAssembly] Forbid use of EM_ASM with setjmp/longjmp · b1cb9fd1
  Guanzhong Chen authored Aug 16, 2019
  b1cb9fd1
- [X86] resolveTargetShuffleInputs - add DemandedElts variant. NFCI. · 63b78b67
  Simon Pilgrim authored Aug 16, 2019
  63b78b67
- [X86] combineExtractWithShuffle - handle extract(truncate(x), 0) · 8ff1b7de
  Simon Pilgrim authored Aug 16, 2019
  8ff1b7de
- [AArch64InstrInfo] Stop getInstSizeInBytes returning non-zero for meta instructions. · 2632c677
  Paul Walker authored Aug 16, 2019
  2632c677
- Revert [AArch64InstrInfo] Stop getInstSizeInBytes returning non-zero for meta instructions. · 19301d75
  Paul Walker authored Aug 16, 2019
  19301d75
- [X86] Alphabetize pass initialization definitions. NFCI. · 3a8c6987
  Simon Pilgrim authored Aug 16, 2019
  3a8c6987
- [Hexagon] Generate min/max instructions for 64-bit vectors · ac83aab0
  Krzysztof Parzyszek authored Aug 16, 2019
  ac83aab0
- Relanding r368987 [AArch64] Change location of frame-record within callee-save area. · f28e1128
  Sander de Smalen authored Aug 16, 2019
  f28e1128
- [ARM] MVE sext of a load is free · b782e61e
  David Green authored Aug 16, 2019
  b782e61e
- [RISCV] Convert registers from unsigned to Register · fa06e958
  Luis Marques authored Aug 16, 2019
  fa06e958
- [AArch64InstrInfo] Stop getInstSizeInBytes returning non-zero for meta instructions. · 3ccee5f7
  Paul Walker authored Aug 16, 2019
  3ccee5f7
- [X86] Remove unused include. NFCI. · 9da4989c
  Simon Pilgrim authored Aug 16, 2019
  9da4989c
- [ARM] Correct register for narrowing and widening MVE loads and stores. · 6e1ac424
  David Green authored Aug 16, 2019
  6e1ac424
- [ARM] Don't pretend we know how to generate MVE VLDn · 8c2c5f50
  David Green authored Aug 16, 2019
  8c2c5f50
- [RISCV] Allow parsing of bare symbols with offsets · d3f774d3
  Lewis Revill authored Aug 16, 2019
  d3f774d3
- [RISCV] Lower inline asm constraint A for RISC-V · 7abf863f
  Lewis Revill authored Aug 16, 2019
  7abf863f