Commits · f4df554f32ab1998a75e4c83f3219896970ce3a6 · Roger Ferrer / llvm-epi · GitLab

Jun 01, 2018
- [mips] Guard 'nop' properly and add mips16's nop instruction · 54217598
  Simon Dardis authored Jun 01, 2018
  54217598
- [AArch64][SVE] Asm: Support for DUPM (masked immediate) instruction. · 97ca6b9e
  Sander de Smalen authored Jun 01, 2018
  97ca6b9e
- [X86][Disassembler] Make it an error to set EVEX.R' to 0 when modrm.reg encodes a GPR. · c3cf55b9
  Craig Topper authored Jun 01, 2018
  c3cf55b9
- [X86][Disassembler] Ignore EVEX.X extension of modrm.rm to 5-bits when... · 0838c4d6
  Craig Topper authored Jun 01, 2018
  0838c4d6
- Implemented sane default for llvm-objdump's relocation Value format · d72b9fd1
  Daniel Cederman authored Jun 01, 2018
  d72b9fd1
- [X86][Disassembler] Clamp index to 4-bits when decoding GPR registers. · 74a61b02
  Craig Topper authored Jun 01, 2018
  74a61b02
- [X86] Add a test case showing a bad disassembling of an EVEX instruction with... · 1a00b0ac
  Craig Topper authored Jun 01, 2018
  1a00b0ac
- [X86][Disassembler] Make sure EVEX.X is not used to extend base registers of memory operations. · 5b1dd01e
  Craig Topper authored Jun 01, 2018
  5b1dd01e
- [X86] Make sure the check for VEX.vvvv being all ones on instructions that... · dc5ba1e4
  Craig Topper authored Jun 01, 2018
  dc5ba1e4
- [X86][Disassembler] Suppress reading of EVEX.V' and EVEX.R' in 32-bit mode. · 0179c6d0
  Craig Topper authored Jun 01, 2018
  0179c6d0
- [X86] Add test cases showing the disassembler producing an xmm16-xmm31 register in 32-bit mode. · b9c2e8cc
  Craig Topper authored Jun 01, 2018
  b9c2e8cc
May 31, 2018
- [MC] Fallback on DWARF when generating compact unwind on AArch64 · 90aba024
  Francis Visoiu Mistrih authored May 31, 2018
  90aba024
- [mips] Guard all short instructions correctly. · d9a45383
  Simon Dardis authored May 31, 2018
  d9a45383
May 30, 2018
- [mips] Correct the predicates of arithmetic and logic instructions. · 39710e35
  Simon Dardis authored May 30, 2018
  39710e35
- AArch64: print correct annotation for ADRP addresses. · d8949f50
  Tim Northover authored May 30, 2018
  d8949f50
- [AArch64][AsmParser] Fix segfault on illegal fpimm. · bdf09fe7
  Sander de Smalen authored May 30, 2018
  bdf09fe7
- [WebAssembly] MC: Add compile-twice test and fix corresponding bug · 105bdc25
  Sam Clegg authored May 30, 2018
  105bdc25
- [RISCV] Support resolving fixup_riscv_call and add to MCFixupKindInfo table · c3d0e892
  Shiva Chen authored May 30, 2018
  c3d0e892
May 29, 2018
- [mips] Process numeric register name in the .set assignment directive · 69301c9e
  Simon Atanasyan authored May 29, 2018
  69301c9e
- [AArch64][SVE] Asm: Support for predicated LSL/LSR (vectors) · 8704b03c
  Sander de Smalen authored May 29, 2018
  8704b03c
- [CodeView] Add prefix to CodeView registers. · 43dce3ed
  Jonas Devlieghere authored May 29, 2018
  43dce3ed
- [AArch64][SVE] Asm: Support for AND, ORR, EOR and BIC instructions. · 26b9b2a8
  Sander de Smalen authored May 29, 2018
  26b9b2a8
- [mips] Emit R_MICROMIPS_GPREL16/R_MICROMIPS_SUB/R_MICROMIPS_LO16 / HI16 relocations · a1d69f9e
  Simon Atanasyan authored May 29, 2018
  a1d69f9e
- [AArch64][SVE] Asm: Support for ADD (immediate) instructions. · 98686c6b
  Sander de Smalen authored May 29, 2018
  98686c6b
- [mips] Emit R_MICROMIPS_HIGHER / R_MICROMIPS_HIGHEST relocations · 6be87bce
  Simon Atanasyan authored May 29, 2018
  6be87bce
- [mips] Correct the predicates for a number of instructions. · 0fad58cb
  Simon Dardis authored May 29, 2018
  0fad58cb
- [mips] Stop parsing a .set assignment if the first argument is not an identifier · 3535cb11
  Simon Atanasyan authored May 29, 2018
  3535cb11
May 28, 2018
- [PowerPC] Set isAsmParserOnly=1 for X-form TLS loads/stores · 6f3df02f
  Zaara Syeda authored May 28, 2018
  6f3df02f
- [Sparc] Add .uahalf and .uaword directives · 2e7fe0ed
  Daniel Cederman authored May 28, 2018
  2e7fe0ed
May 25, 2018
- [AArch64][SVE] Asm: Support for DUP (immediate) instructions. · 62770795
  Sander de Smalen authored May 25, 2018
  62770795
May 24, 2018
- [RISCV] Support linker relax function call from auipc and jalr to jal · 43bfe844
  Shiva Chen authored May 24, 2018
  43bfe844
May 23, 2018
- [RISCV] Add symbol diff relocation support for RISC-V · 257d5b56
  Alex Bradbury authored May 23, 2018
  257d5b56
- [Sparc] Add mnemonic aliases for flush, stb, stba, sth, and stha · 6356571e
  Daniel Cederman authored May 23, 2018
  6356571e
May 22, 2018
- [mips] Correct the predicates of the cache and pref instructions · 437153bb
  Simon Dardis authored May 22, 2018
  437153bb
May 21, 2018
- MC: Introduce an ELF dwo object writer and teach llvm-mc about it. · 63062d9d
  Peter Collingbourne authored May 21, 2018
  63062d9d
May 20, 2018
- [mips] Add microMIPSR6 ll/sc instructions. · 777afc7f
  Simon Dardis authored May 20, 2018
  777afc7f
May 18, 2018
- [MC] Relax .fill size requirements · 588fad4d
  Nirav Dave authored May 18, 2018
  588fad4d
- [RISCV] Add WasForced parameter to MCAsmBackend::fixupNeedsRelaxationAdvanced · 6e07dfb1
  Shiva Chen authored May 18, 2018
  6e07dfb1
May 17, 2018
- [RISCV] Implement MC layer support for the tail pseudoinstruction · ef0ebf28
  Mandeep Singh Grang authored May 17, 2018
  ef0ebf28
- [mips] Add support for Global INValidate ASE · daf51693
  Petar Jovanovic authored May 17, 2018
  daf51693