Commits · f5e2ea9a43221be9576056c4912796cf37331cd7 · Roger Ferrer / llvm-epi · GitLab

Sep 03, 2020
- [AArch64] Add asm directives for the remaining SEH unwind codes · f5e2ea9a
  Martin Storsjö authored Aug 16, 2020
  f5e2ea9a
Sep 02, 2020
- [AMDGPU][MC] Corrected parser to avoid generation of excessive error messages · ecde2002
  Dmitry Preobrazhensky authored Sep 02, 2020
  ecde2002
Sep 01, 2020
- [PowerPC] Implement instruction definitions/MC Tests for xvcvspbf16 and xvcvbf16spn · ca2227c1
  Amy Kwan authored Sep 01, 2020
  ca2227c1
Aug 29, 2020
- [AArch64] Generate and parse SEH assembly directives · 5b86d130
  Martin Storsjö authored Aug 07, 2020
  5b86d130
- [MC] [Win64EH] Fill in FuncletOrFuncEnd if missing · 20f7773b
  Martin Storsjö authored Aug 20, 2020
  20f7773b
Aug 28, 2020
- [MC] [Win64EH] Avoid producing malformed xdata records · 37ef743c
  Martin Storsjö authored Aug 20, 2020
  37ef743c
Aug 27, 2020
- [RISCV] add the MC layer support of riscv vector Zvamo extension · 888c02de
  luxufan authored Jul 31, 2020
  888c02de
Aug 26, 2020
- [MC][SVE] Fix data operand for instruction alias of `st1d`. · 61dfa009
  Francesco Petrogalli authored Aug 26, 2020
  61dfa009
- [X86] Add assembler support for .d32 and .d8 mnemonic suffixes to control displacement size. · 09288bcb
  Craig Topper authored Aug 26, 2020
  09288bcb
- [MC] [Win64EH] Update the AArch64/seh.s test slightly. NFC. · b07d78bc
  Martin Storsjö authored Aug 20, 2020
  b07d78bc
Aug 21, 2020
- [PowerPC][PCRelative] Thread Local Storage Support for Initial Exec · 365f861c
  Kamau Bridgeman authored Jun 16, 2020
  365f861c
Aug 20, 2020
- [PowerPC][PCRelative] Thread Local Storage Support for General Dynamic · b74b80bb
  Kamau Bridgeman authored Jun 22, 2020
  b74b80bb
Aug 19, 2020
- [RISCV] add the assemble and disassemble support of Zvlsseg instructions · 6c5039a1
  luxufan authored Jul 23, 2020
  6c5039a1
Aug 17, 2020
- [RISCV] Enable the use of the old mucounteren name · 3f7068ad
  Sam Elliott authored Aug 17, 2020
  3f7068ad
Aug 15, 2020
- AMDGPU: Fix global atomic saddr operand class · a7455652
  Matt Arsenault authored Aug 14, 2020
  
  a7455652
- AMDGPU: Correct definitions for global saddr instructions · 47af1ac6
  Matt Arsenault authored Aug 11, 2020
  47af1ac6
Aug 12, 2020
- [WebAssembly][AsmParser] Name missing features in error message · 2985c02f
  Thomas Lively authored Aug 11, 2020
  2985c02f
Aug 11, 2020
- [AARCH64] [MC] add memtag as an alias of mte architecture extension · 277873ce
  Jian Cai authored Aug 11, 2020
  277873ce
Aug 07, 2020
- Revert "Reland D64327 [MC][ELF] Allow STT_SECTION referencing SHF_MERGE on REL targets" · 382df1c6
  Mitch Phillips authored Aug 07, 2020
  382df1c6
- [PowerPC] Add Vector Extract/Expand/Count with Mask, Move to VSR Mask... · 98eccec3
  Amy Kwan authored Aug 06, 2020
  98eccec3
Aug 06, 2020
- [AArch64] [Windows] Error out on unsupported symbol locations · f5e6fbac
  Martin Storsjö authored Aug 04, 2020
  f5e6fbac
Aug 05, 2020
- [AMDGPU] gfx1031 target · ea7d0e29
  Stanislav Mekhanoshin authored Aug 05, 2020
  ea7d0e29
Aug 03, 2020
- [WebAssembly] Implement prototype v128.load{32,64}_zero instructions · cb327922
  Thomas Lively authored Aug 03, 2020
  cb327922
- [MC] Set sh_link to 0 if the associated symbol is undefined · 11bb7c22
  Fangrui Song authored Aug 03, 2020
  11bb7c22
- [X86] support .nops directive · c6334db5
  Jian Cai authored Jul 30, 2020
  c6334db5
- Reland D64327 [MC][ELF] Allow STT_SECTION referencing SHF_MERGE on REL targets · b497665d
  Fangrui Song authored Aug 02, 2020
  b497665d
Aug 01, 2020
- [X86] Add assembler support for {disp8} and {disp32} to control the size of... · e297d928
  Craig Topper authored Aug 01, 2020
  e297d928
- Upgrade MC to v0.9. · 47a4a27f
  Hsiangkai Wang authored May 21, 2020
  47a4a27f
Jul 31, 2020
- [PowerPC] Add Vector String Isolate instruction definitions and MC Tests · 93fd8dbd
  Albion Fung authored Jul 31, 2020
  93fd8dbd
- [MC] Support infix operator ! · 1cc21038
  Fangrui Song authored Jul 30, 2020
  1cc21038
Jul 30, 2020
- [X86] Parse and ignore .arch directives · d2c22487
  Fangrui Song authored Jul 30, 2020
  d2c22487
- [X86] Teach the assembler parser to handle a '*' between segment register and... · 9611ee5f
  Craig Topper authored Jul 29, 2020
  9611ee5f
Jul 28, 2020
- Re-land "[PowerPC] Remove QPX/A2Q BGQ/BGP CNK support" · d28f8672
  Jinsong Ji authored Jul 28, 2020
  d28f8672
- [PowerPC] Split s34imm into two types · 97470897
  Stefan Pintilie authored Jul 27, 2020
  97470897
- [X86] Add support for {disp32} to control size of jmp and jcc instructions in the assembler · 25f193fb
  Craig Topper authored Jul 27, 2020
  25f193fb
- [X86] Properly encode a 32-bit address with an index register and no base register in 16-bit mode. · a0ebac52
  Craig Topper authored Jul 27, 2020
  a0ebac52
Jul 27, 2020
- Revert "[PowerPC] Remove QPX/A2Q BGQ/BGP CNK support" · bf544fa1
  Jinsong Ji authored Jul 27, 2020
  bf544fa1
- [PowerPC] Remove QPX/A2Q BGQ/BGP CNK support · adffce71
  Jinsong Ji authored Jul 27, 2020
  adffce71
- AArch64: diagnose out of range relocation addends on MachO. · 216b67e2
  Tim Northover authored Jul 22, 2020
  216b67e2
- [PowerPC] Add Vector Extract Double Instruction Definitions and MC tests. · 825ed2d4
  biplmish authored Jul 26, 2020
  825ed2d4