Commits · f63405f6e3d30f33e715ef5ad09136127535a3fb · Roger Ferrer / llvm-epi · GitLab

Nov 01, 2021
- BPF: Workaround an InstCombine ICmp transformation with llvm.bpf.compare builtin · f63405f6
  Yonghong Song authored Oct 30, 2021
  f63405f6
- [RISCV] Restore tests for vf(w)redusum. · 670c72f6
  Craig Topper authored Nov 01, 2021
  670c72f6
- [SVE] Fix VLS FMA matching for CodeGenOpt::Aggressive. · 702fd3d3
  Cameron McInally authored Nov 01, 2021
  702fd3d3
- [NFC][PowerPC] Update testcases using script · bd932f74
  Jinsong Ji authored Nov 01, 2021
  bd932f74
- [AMDGPU] Add tests for legacy multiply-add with immediate · b85995f6
  Jay Foad authored Nov 01, 2021
  
  b85995f6
- [AMDGPU] Shrink v_mac_legacy_f32 and v_fmac_legacy_f32 · 2b548b18
  Jay Foad authored Nov 01, 2021
  2b548b18
- [X86][AVX] Prefer VINSERTF128 over VPERM2F128 for 128->256 subvector concatenations · fd485d8c
  Simon Pilgrim authored Nov 01, 2021
  fd485d8c
- [Taildup] Don't tail-duplicate loop header with multiple successors as its latches · 1f9fa549
  Jun Ma authored Sep 28, 2021
  1f9fa549
- [TailDup] Add testcase for interpreter switch loop, NFC. · f8833ba1
  Jun Ma authored Sep 29, 2021
  
  f8833ba1
- [PowerPC] turn off chain commoning by default. · eeed1545
  Chen Zheng authored Nov 01, 2021
  
  eeed1545
- [Verifier] Add verification logic for GlobalIFuncs · 848812a5
  Itay Bookstein authored Oct 31, 2021
  848812a5
- [CSKY] First patch to construct codegen infra and generate first add instruction · cf78715c
  Zi Xuan Wu authored Nov 01, 2021
  cf78715c
Oct 31, 2021
- [RISCV] Expand scalable vector bswap. Fix crash for bitreverse. · ada54585
  Craig Topper authored Oct 29, 2021
  ada54585
Oct 30, 2021
- [ValueTracking] Teach computeConstantRange that the maximum value of a half is 65504 · 2c4a9e83
  David Green authored Oct 30, 2021
  2c4a9e83
- GlobalISel/Utils: Use incoming regbank while constraining the superclasses · aa2d3b59
  Christudasan Devadasan authored Oct 22, 2021
  aa2d3b59
- [ARM] Add some fp convert with saturate MVE tests. NFC · 1ad9b072
  David Green authored Oct 30, 2021
  
  1ad9b072
- [X86][NFC] Pre-commit test to show prolog insert problem · 134c3082
  Phoebe Wang authored Oct 30, 2021
  
  134c3082
Oct 29, 2021
- [AMDGPU] Fix global isel for kernels using agprs on gfx90a · e5340ed3
  Stanislav Mekhanoshin authored Oct 27, 2021
  e5340ed3
- [SparcISelLowering] avoid emitting libcalls to __muloti4 and __mulodi4 · 39e5dd11
  Nick Desaulniers authored Oct 29, 2021
  39e5dd11
- [x86] limit vector increment fold to allow load folding · 285b8abc
  Sanjay Patel authored Oct 29, 2021
  285b8abc
- [AArch64][GlobalISel] Fix an crash in RBS due to a new regclass being added. · 5dd9e019
  Amara Emerson authored Oct 29, 2021
  5dd9e019
- [X86] Don't affect jump tables under +tagged-globals. · 33cc0cfd
  Matt Morehouse authored Oct 29, 2021
  33cc0cfd
- [RISCV] Teach RISCVInsertVSETVLI::needVSETVLI to handle mask register instructions better. · aefcd598
  Craig Topper authored Oct 28, 2021
  aefcd598
- AMDGPU: Check kernarg alignments in test · 52fc2edb
  Matt Arsenault authored Oct 27, 2021
  52fc2edb
- [AArch64][SVE] Use TargetFrameIndex in more SVE load/store addressing modes · 86972f11
  Bradley Smith authored Oct 26, 2021
  86972f11
- [X86] combineX86GatherScatter - only fold scale if the index isn't extended · 154c036e
  Simon Pilgrim authored Oct 29, 2021
  154c036e
- [TailDuplicator] Fix merging block with terminator · c78640ee
  Neubauer, Sebastian authored Oct 22, 2021
  c78640ee
- [AMDGPU] Fix cvt_f32_ubyte combine with shl · 52b43d15
  Vang Thao authored Oct 28, 2021
  52b43d15
- [RISCV] Add a test case showing unnecessary vsetvli for mask register instructions. · 67c44a99
  Craig Topper authored Oct 28, 2021
  67c44a99
Oct 28, 2021
- [WebAssembly] Add prototype relaxed float to int trunc instructions · fb67f3d9
  Thomas Lively authored Oct 28, 2021
  fb67f3d9
- Reland "[ARM] __cxa_end_cleanup should be called instead of _UnwindResume." · d8075e87
  Daniel Kiss authored Oct 27, 2021
  d8075e87
- [TwoAddressInstructionPass] Put all new instructions into DistanceMap · 1e46dcb7
  Guozhi Wei authored Oct 28, 2021
  1e46dcb7
- X86InstrInfo: Support immediates that are +1/-1 different in optimizeCompareInstr · e2c7ee07
  Matthias Braun authored Sep 27, 2021
  e2c7ee07
- X86InstrInfo: Optimize more combinations of SUB+CMP · 97a1570d
  Matthias Braun authored Sep 27, 2021
  97a1570d
- [PowerPC][NFC] Update builtins-ppc-xlcompat-trap-64bit-only.ll and... · 40cad47f
  Victor Huang authored Oct 28, 2021
  40cad47f
- Revert "Reland "[ARM] __cxa_end_cleanup should be called instead of _UnwindResume."" · 66e03db8
  Daniel Kiss authored Oct 28, 2021
  66e03db8
- Reland "[ARM] __cxa_end_cleanup should be called instead of _UnwindResume." · b6420e57
  Daniel Kiss authored Oct 27, 2021
  b6420e57
- [X86][AVX] Attempt to fold a scaled index into a gather/scatter scale immediate (PR13310) · d29ccbec
  Simon Pilgrim authored Oct 28, 2021
  d29ccbec
- [AMDGPU] Add 24-bit mulhi intrinsics in INTRINSIC_WO_CHAIN combine. · 2da6ef36
  Abinav Puthan Purayil authored Oct 28, 2021
  2da6ef36
- [AMDGPU] Fix rhs of the tests in amdgpu-codegenprepare-mul24.ll. · 9f8e779b
  Abinav Puthan Purayil authored Oct 28, 2021
  9f8e779b