Commits · f76fe454268d661cb31018d9e46a6df467bb22b9 · Roger Ferrer / llvm-epi · GitLab

Apr 02, 2019
- [SystemZ] Improve instruction selection of 64 bit shifts and rotates. · f76fe454
  Jonas Paulsson authored Apr 02, 2019
  f76fe454
- [mips] Remove the override of the `isMachineVerifierClean()` · 4cefa15a
  Simon Atanasyan authored Apr 02, 2019
  4cefa15a
- [mips] Use AltOrders to prevent using odd FP-registers · 2634a141
  Simon Atanasyan authored Apr 02, 2019
  2634a141
- [RISCV] Support assembling @plt symbol operands · f8078f6b
  Alex Bradbury authored Apr 02, 2019
  f8078f6b
- Enforce StackID definition in PEI · 7f23e0a6
  Sander de Smalen authored Apr 02, 2019
  7f23e0a6
- [X86] Use unsigned type for opcodes throughout X86FixupLEAs. · c5903c93
  Craig Topper authored Apr 02, 2019
  c5903c93
- [ARM] Optimize expressions like "return x != 0;" for Thumb1. · 3813fe0b
  Eli Friedman authored Apr 02, 2019
  3813fe0b
- [ARM] Don't try to create "push {r12, lr}" in Thumb1 at -Oz. · 73af6ef2
  Eli Friedman authored Apr 01, 2019
  73af6ef2
- [AArch64][GlobalISe] Select STRQui for stores into v264s instead of scalarizing · e44c20a6
  Jessica Paquette authored Apr 01, 2019
  e44c20a6
Apr 01, 2019
- [X86] Classify the AVX512 rounding control operand as... · 4307172b
  Craig Topper authored Apr 01, 2019
  4307172b
- [NVPTX] Fix the codegen for llvm.round. · 6c21ccd2
  Bixia Zheng authored Apr 01, 2019
  6c21ccd2
- [AMDGPU] Pre-allocate WWM registers to reduce VGPR pressure. · 0a30f33c
  Neil Henning authored Apr 01, 2019
  0a30f33c
- [AArch64] Add v8.5-a Memory Tagging STZGM instruction · 3d233d5d
  David Spickett authored Apr 01, 2019
  3d233d5d
- [RISCV] Attach VK_RISCV_CALL to symbols upon creation · 44668ae7
  Alex Bradbury authored Apr 01, 2019
  44668ae7
- [AArch64] Add v8.5-a Memory Tagging STGM/LDGM instructions · 9142b8ef
  David Spickett authored Apr 01, 2019
  9142b8ef
- [RISCV] Generate address sequences suitable for mcmodel=medium · da20f5ca
  Alex Bradbury authored Apr 01, 2019
  da20f5ca
- [AArch64] Add v8.5-a Memory Tagging GMID_EL1 register · efe376ad
  David Spickett authored Apr 01, 2019
  efe376ad
- X86: Fix override warning · ebf90db0
  Matt Arsenault authored Apr 01, 2019
  ebf90db0
- [X86] Make post-ra scheduling macrofusion-aware. · 7e062c9b
  Clement Courbet authored Apr 01, 2019
  7e062c9b
- [RISCV] Add seto pattern expansion · 3091884e
  Luis Marques authored Apr 01, 2019
  3091884e
- [X86] Use ISD::INTRINSIC_VOID in getTgtMemIntrinsic for truncating stores and scatter intrinsics. · 2e1bf89e
  Craig Topper authored Apr 01, 2019
  2e1bf89e
- [RISCV] Don't evaluatePCRelLo if a relocation will be forced (e.g. due to linker relaxation) · ca81a56f
  Alex Bradbury authored Apr 01, 2019
  ca81a56f
Mar 31, 2019
- [x86] allow movmsk with 2-element reductions · e1bc360f
  Sanjay Patel authored Mar 31, 2019
  e1bc360f
- fix typo: "\t" => " " · 9f4a4d39
  Liang Zou authored Mar 31, 2019
  9f4a4d39
Mar 30, 2019
- [X86] Teach isel for RMW binops to handle negate · e4a0fc7d
  Craig Topper authored Mar 30, 2019
  e4a0fc7d
- [RISCV] Add codegen support for ilp32f, ilp32d, lp64f, and lp64d ("hard float") ABIs · 0b2803ee
  Alex Bradbury authored Mar 30, 2019
  0b2803ee
- [X86][SSE] detectAVGPattern - Match zext(or(x,y)) 'add like' patterns (PR41316) · 10c9032c
  Simon Pilgrim authored Mar 30, 2019
  10c9032c
- [X86][SSE] detectAVGPattern - begin generalizing ADD matches · 32934555
  Simon Pilgrim authored Mar 30, 2019
  32934555
- [WebAssembly] Fix unwind destination mismatches in CFG stackify · c4ac74fb
  Heejin Ahn authored Mar 30, 2019
  c4ac74fb
- [WebAssembly] Run ExplicitLocals pass after CFGStackify · e9fd9073
  Heejin Ahn authored Mar 30, 2019
  e9fd9073
- [RISCV] Add DAGCombine for (SplitF64 (ConstantFP x)) · 9681b01c
  Alex Bradbury authored Mar 30, 2019
  9681b01c
- [WebAssembly] Optimize the number of routing blocks in FixIrreducibleCFG · 7e7aad15
  Heejin Ahn authored Mar 30, 2019
  7e7aad15
Mar 29, 2019
- [WebAssembly] Add mutable globals feature · 5f0c4c67
  Thomas Lively authored Mar 29, 2019
  5f0c4c67
- [GlobalISel][AArch64] Add isel support for G_INSERT_VECTOR_ELT on v2s32s · d3ffd47d
  Jessica Paquette authored Mar 29, 2019
  d3ffd47d
- [X86] When using Win64 ABI, exit with error if SSE is disabled for varargs · d413f41d
  Amara Emerson authored Mar 29, 2019
  d413f41d
- [WebAssembly] Handle END_LOOP in unreachable BB in CFGStackify · 67f74ace
  Heejin Ahn authored Mar 29, 2019
  67f74ace
- AMDGPU: Remove dx10-clamp from subtarget features · 055e4dce
  Matt Arsenault authored Mar 29, 2019
  055e4dce
- [X86] Use cached OptForSize in X86ISelDAGToDAG.cpp instead of pulling it from... · 4ccb3b96
  Craig Topper authored Mar 29, 2019
  4ccb3b96
- [CodeGen] Refactor the option for the maximum jump table size · 0f797b87
  Evandro Menezes authored Mar 29, 2019
  0f797b87
- [mips] Fix lowering a signed immediate for *.d MSA instructions · f26f56d6
  Simon Atanasyan authored Mar 29, 2019
  f26f56d6