Commits · f84bc3793e9d1ba170a35b1909dd1057b63c2f15 · Roger Ferrer / llvm-epi · GitLab

May 05, 2018
- [globalisel] Update GlobalISel emitter to match new representation of extending loads · f84bc379
  Daniel Sanders authored May 05, 2018
  f84bc379
- [MIRPraser] Improve error checking for typed immediate operands · c86da6bc
  Heejin Ahn authored May 05, 2018
  c86da6bc
- [DAGCombiner] Masked merge: don't touch "not" xor's. · a3b0b59f
  Roman Lebedev authored May 05, 2018
  a3b0b59f
- [MIRParser] Allow register class names in the form of integer/scalar · c2ad0968
  Heejin Ahn authored May 05, 2018
  c2ad0968
- Mapping SDNode flags to MachineInstr flags · 2dcf12ff
  Michael Berg authored May 04, 2018
  2dcf12ff
May 04, 2018
- AMDGPU: Add D16 instructions preserve unused bits feature · c2c2eb7d
  Konstantin Zhuravlyov authored May 04, 2018
  c2c2eb7d
- [MachineLICM] Debug intrinsics shouldn't affect hoist decisions · 8e4958e7
  Geoff Berry authored May 04, 2018
  8e4958e7
- Fast Math Flag mapping into SDNode · 7acc81b7
  Michael Berg authored May 04, 2018
  7acc81b7
- [X86] Add WriteEMMS scheduler class · 0e51a125
  Simon Pilgrim authored May 04, 2018
  0e51a125
- [X86] Finish splitting WriteVecShift and WriteVecIMul to remove InstRW overrides. · d7ffbc5c
  Simon Pilgrim authored May 04, 2018
  d7ffbc5c
- [AArch64] Add missing testcase for r331522 · 6d56294c
  Adhemerval Zanella authored May 04, 2018
  6d56294c
- [Hexagon] Handle non-immediate constants in HexagonSplitDouble · effcc2fb
  Krzysztof Parzyszek authored May 04, 2018
  effcc2fb
- [AArch64] Custom Lower MULLH{S,U} for v16i8, v8i16, and v4i32 · a57ef17a
  Adhemerval Zanella authored May 04, 2018
  a57ef17a
- [Hexagon] Skip reserved physical registers when updating liveness · af73d2bd
  Krzysztof Parzyszek authored May 04, 2018
  af73d2bd
- [X86] Add test case for PR30290s failing behaviour · 07e8daa6
  Jeremy Morse authored May 04, 2018
  07e8daa6
- Word wrap a test-file comment to 80 columns · 71f17bf8
  Jeremy Morse authored May 04, 2018
  71f17bf8
- [RegUsageInfoCollector] Bugfix for handling of register aliases. · 72fe7605
  Jonas Paulsson authored May 04, 2018
  72fe7605
- [X86][Znver1] Use SchedAlias to tag microcoded scheduler classes · 0aed7315
  Simon Pilgrim authored May 03, 2018
  0aed7315
May 03, 2018
- [PowerPC] add more FMF debug output; NFC · 52151885
  Sanjay Patel authored May 03, 2018
  52151885
- [X86] Split WriteVecShift/WriteVarVecShift into MMX, XMM and YMM/ZMM scheduler classes · f2d2ceda
  Simon Pilgrim authored May 03, 2018
  f2d2ceda
- [PowerPC] add tests for FMF propagation; NFC · e7532d29
  Sanjay Patel authored May 03, 2018
  e7532d29
- [CodeGen][X86][NFC] Copy two selectcc tests from AArch64. · 63ac1936
  Roman Lebedev authored May 03, 2018
  63ac1936
- [X86] Split WriteVecALU/WritePHAdd into XMM and YMM/ZMM scheduler classes · f7dd6069
  Simon Pilgrim authored May 03, 2018
  f7dd6069
- ARM: don't try to over-align large vectors as arguments. · 28e0a6f7
  Tim Northover authored May 03, 2018
  28e0a6f7
- Rename invariant.group.barrier to launder.invariant.group · 5dde8094
  Piotr Padlewski authored May 03, 2018
  5dde8094
- [X86] Split WriteVecIMul/WriteVecPMULLD/WriteMPSAD/WritePSADBW into XMM and... · 93c878c7
  Simon Pilgrim authored May 03, 2018
  93c878c7
- MachineInst support mapping SDNode fast math flags for support in Back End code generation · 7d1b25d0
  Michael Berg authored May 03, 2018
  7d1b25d0
- [PowerPC] Implement isMaskAndCmp0FoldingBeneficial · 01e2e79a
  Nemanja Ivanovic authored May 02, 2018
  01e2e79a
- [PowerPC] No CTR loop if the candidate exiting block is in a different loop · 2139e99e
  Nemanja Ivanovic authored May 02, 2018
  2139e99e
May 02, 2018
- [X86][SNB] Fix scheduling of MMX integer multiply instructions. · 350c22c5
  Simon Pilgrim authored May 02, 2018
  350c22c5
- [X86] Split WriteShuffle/WriteVarShuffle + WriteBlend/WriteVarBlend into XMM... · 6732f6ea
  Simon Pilgrim authored May 02, 2018
  6732f6ea
- [AMDGPU] A trivial fix for a buildbot failure caused by "commit... · 07e61234
  Farhana Aleen authored May 02, 2018
  07e61234
- [X86] Cleanup WriteFShuffle/WriteFVarShuffle (+256 variants) scheduler classes... · 819f218f
  Simon Pilgrim authored May 02, 2018
  819f218f
- Revert "[AMDGPU] performAddCombine should run after DAG is legalized." · 150cb6d9
  Farhana Aleen authored May 02, 2018
  150cb6d9
- [AMDGPU] performAddCombine should run after DAG is legalized. · 2f4100f5
  Farhana Aleen authored May 02, 2018
  2f4100f5
- [X86] Cleanup WriteFAdd/WriteFCmp scheduler classes with more common default values · e93fd5f1
  Simon Pilgrim authored May 02, 2018
  e93fd5f1
May 01, 2018
- [AMDGPU] Support horizontal vectorization. · e2dfe8a8
  Farhana Aleen authored May 01, 2018
  e2dfe8a8
- [AArch64] Add more tests for 64-bit immediate lowering. · 763d161e
  Eli Friedman authored May 01, 2018
  763d161e
- [DAGCombiner] Fix SDLoc in a (zext (zextload x)) combine (4/N) · e23173b6
  Vedant Kumar authored May 01, 2018
  e23173b6
- [DAGCombiner] Fix SDLoc in a (sext (sextload x)) combine (3/N) · d7117ed0
  Vedant Kumar authored May 01, 2018
  d7117ed0